1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2# Copyright (C) 2020 SiFive, Inc.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/interrupt-controller/sifive,plic-1.0.0.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: SiFive Platform-Level Interrupt Controller (PLIC)
9
10description:
11  SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
12  (PLIC) high-level specification in the RISC-V Privileged Architecture
13  specification. The PLIC connects all external interrupts in the system to all
14  hart contexts in the system, via the external interrupt source in each hart.
15
16  A hart context is a privilege mode in a hardware execution thread. For example,
17  in an 4 core system with 2-way SMT, you have 8 harts and probably at least two
18  privilege modes per hart; machine mode and supervisor mode.
19
20  Each interrupt can be enabled on per-context basis. Any context can claim
21  a pending enabled interrupt and then release it once it has been handled.
22
23  Each interrupt has a configurable priority. Higher priority interrupts are
24  serviced first.  Each context can specify a priority threshold. Interrupts
25  with priority below this threshold will not cause the PLIC to raise its
26  interrupt line leading to the context.
27
28  While the PLIC supports both edge-triggered and level-triggered interrupts,
29  interrupt handlers are oblivious to this distinction and therefore it is not
30  specified in the PLIC device-tree binding.
31
32  While the RISC-V ISA doesn't specify a memory layout for the PLIC, the
33  "sifive,plic-1.0.0" device is a concrete implementation of the PLIC that
34  contains a specific memory layout, which is documented in chapter 8 of the
35  SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>.
36
37maintainers:
38  - Sagar Kadam <sagar.kadam@sifive.com>
39  - Paul Walmsley  <paul.walmsley@sifive.com>
40  - Palmer Dabbelt <palmer@dabbelt.com>
41
42properties:
43  compatible:
44    items:
45      - const: sifive,fu540-c000-plic
46      - const: sifive,plic-1.0.0
47
48  reg:
49    maxItems: 1
50
51  '#address-cells':
52    const: 0
53
54  '#interrupt-cells':
55    const: 1
56
57  interrupt-controller: true
58
59  interrupts-extended:
60    minItems: 1
61    description:
62      Specifies which contexts are connected to the PLIC, with "-1" specifying
63      that a context is not present. Each node pointed to should be a
64      riscv,cpu-intc node, which has a riscv node as parent.
65
66  riscv,ndev:
67    $ref: "/schemas/types.yaml#/definitions/uint32"
68    description:
69      Specifies how many external interrupts are supported by this controller.
70
71required:
72  - compatible
73  - '#address-cells'
74  - '#interrupt-cells'
75  - interrupt-controller
76  - reg
77  - interrupts-extended
78  - riscv,ndev
79
80additionalProperties: false
81
82examples:
83  - |
84    plic: interrupt-controller@c000000 {
85      #address-cells = <0>;
86      #interrupt-cells = <1>;
87      compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
88      interrupt-controller;
89      interrupts-extended = <
90        &cpu0_intc 11
91        &cpu1_intc 11 &cpu1_intc 9
92        &cpu2_intc 11 &cpu2_intc 9
93        &cpu3_intc 11 &cpu3_intc 9
94        &cpu4_intc 11 &cpu4_intc 9>;
95      reg = <0xc000000 0x4000000>;
96      riscv,ndev = <10>;
97    };
98