1*c66ec88fSEmmanuel Vadot* ARC-HS Interrupt Distribution Unit 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel Vadot This optional 2nd level interrupt controller can be used in SMP configurations 4*c66ec88fSEmmanuel Vadot for dynamic IRQ routing, load balancing of common/external IRQs towards core 5*c66ec88fSEmmanuel Vadot intc. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotProperties: 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel Vadot- compatible: "snps,archs-idu-intc" 10*c66ec88fSEmmanuel Vadot- interrupt-controller: This is an interrupt controller. 11*c66ec88fSEmmanuel Vadot- #interrupt-cells: Must be <1> or <2>. 12*c66ec88fSEmmanuel Vadot 13*c66ec88fSEmmanuel Vadot Value of the first cell specifies the "common" IRQ from peripheral to IDU. 14*c66ec88fSEmmanuel Vadot Number N of the particular interrupt line of IDU corresponds to the line N+24 15*c66ec88fSEmmanuel Vadot of the core interrupt controller. 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadot The (optional) second cell specifies any of the following flags: 18*c66ec88fSEmmanuel Vadot - bits[3:0] trigger type and level flags 19*c66ec88fSEmmanuel Vadot 1 = low-to-high edge triggered 20*c66ec88fSEmmanuel Vadot 2 = NOT SUPPORTED (high-to-low edge triggered) 21*c66ec88fSEmmanuel Vadot 4 = active high level-sensitive <<< DEFAULT 22*c66ec88fSEmmanuel Vadot 8 = NOT SUPPORTED (active low level-sensitive) 23*c66ec88fSEmmanuel Vadot When no second cell is specified, the interrupt is assumed to be level 24*c66ec88fSEmmanuel Vadot sensitive. 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel Vadot The interrupt controller is accessed via the special ARC AUX register 27*c66ec88fSEmmanuel Vadot interface, hence "reg" property is not specified. 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel VadotExample: 30*c66ec88fSEmmanuel Vadot core_intc: core-interrupt-controller { 31*c66ec88fSEmmanuel Vadot compatible = "snps,archs-intc"; 32*c66ec88fSEmmanuel Vadot interrupt-controller; 33*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 34*c66ec88fSEmmanuel Vadot }; 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadot idu_intc: idu-interrupt-controller { 37*c66ec88fSEmmanuel Vadot compatible = "snps,archs-idu-intc"; 38*c66ec88fSEmmanuel Vadot interrupt-controller; 39*c66ec88fSEmmanuel Vadot interrupt-parent = <&core_intc>; 40*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 41*c66ec88fSEmmanuel Vadot }; 42*c66ec88fSEmmanuel Vadot 43*c66ec88fSEmmanuel Vadot some_device: serial@c0fc1000 { 44*c66ec88fSEmmanuel Vadot interrupt-parent = <&idu_intc>; 45*c66ec88fSEmmanuel Vadot interrupts = <0>; /* upstream idu IRQ #24 */ 46*c66ec88fSEmmanuel Vadot }; 47