1*c66ec88fSEmmanuel VadotC6X Interrupt Chips 2*c66ec88fSEmmanuel Vadot------------------- 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel Vadot* C64X+ Core Interrupt Controller 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel Vadot The core interrupt controller provides 16 prioritized interrupts to the 7*c66ec88fSEmmanuel Vadot C64X+ core. Priority 0 and 1 are used for reset and NMI respectively. 8*c66ec88fSEmmanuel Vadot Priority 2 and 3 are reserved. Priority 4-15 are used for interrupt 9*c66ec88fSEmmanuel Vadot sources coming from outside the core. 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel Vadot Required properties: 12*c66ec88fSEmmanuel Vadot -------------------- 13*c66ec88fSEmmanuel Vadot - compatible: Should be "ti,c64x+core-pic"; 14*c66ec88fSEmmanuel Vadot - #interrupt-cells: <1> 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadot Interrupt Specifier Definition 17*c66ec88fSEmmanuel Vadot ------------------------------ 18*c66ec88fSEmmanuel Vadot Single cell specifying the core interrupt priority level (4-15) where 19*c66ec88fSEmmanuel Vadot 4 is highest priority and 15 is lowest priority. 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel Vadot Example 22*c66ec88fSEmmanuel Vadot ------- 23*c66ec88fSEmmanuel Vadot core_pic: interrupt-controller@0 { 24*c66ec88fSEmmanuel Vadot interrupt-controller; 25*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 26*c66ec88fSEmmanuel Vadot compatible = "ti,c64x+core-pic"; 27*c66ec88fSEmmanuel Vadot }; 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadot 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel Vadot* C64x+ Megamodule Interrupt Controller 32*c66ec88fSEmmanuel Vadot 33*c66ec88fSEmmanuel Vadot The megamodule PIC consists of four interrupt mupliplexers each of which 34*c66ec88fSEmmanuel Vadot combine up to 32 interrupt inputs into a single interrupt output which 35*c66ec88fSEmmanuel Vadot may be cascaded into the core interrupt controller. The megamodule PIC 36*c66ec88fSEmmanuel Vadot has a total of 12 outputs cascading into the core interrupt controller. 37*c66ec88fSEmmanuel Vadot One for each core interrupt priority level. In addition to the combined 38*c66ec88fSEmmanuel Vadot interrupt sources, individual megamodule interrupts may be cascaded to 39*c66ec88fSEmmanuel Vadot the core interrupt controller. When an individual interrupt is cascaded, 40*c66ec88fSEmmanuel Vadot it is no longer handled through a megamodule interrupt combiner and is 41*c66ec88fSEmmanuel Vadot considered to have the core interrupt controller as the parent. 42*c66ec88fSEmmanuel Vadot 43*c66ec88fSEmmanuel Vadot Required properties: 44*c66ec88fSEmmanuel Vadot -------------------- 45*c66ec88fSEmmanuel Vadot - compatible: "ti,c64x+megamod-pic" 46*c66ec88fSEmmanuel Vadot - interrupt-controller 47*c66ec88fSEmmanuel Vadot - #interrupt-cells: <1> 48*c66ec88fSEmmanuel Vadot - reg: base address and size of register area 49*c66ec88fSEmmanuel Vadot - interrupts: This should have four cells; one for each interrupt combiner. 50*c66ec88fSEmmanuel Vadot The cells contain the core priority interrupt to which the 51*c66ec88fSEmmanuel Vadot corresponding combiner output is wired. 52*c66ec88fSEmmanuel Vadot 53*c66ec88fSEmmanuel Vadot Optional properties: 54*c66ec88fSEmmanuel Vadot -------------------- 55*c66ec88fSEmmanuel Vadot - ti,c64x+megamod-pic-mux: Array of 12 cells correspnding to the 12 core 56*c66ec88fSEmmanuel Vadot priority interrupts. The first cell corresponds to 57*c66ec88fSEmmanuel Vadot core priority 4 and the last cell corresponds to 58*c66ec88fSEmmanuel Vadot core priority 15. The value of each cell is the 59*c66ec88fSEmmanuel Vadot megamodule interrupt source which is MUXed to 60*c66ec88fSEmmanuel Vadot the core interrupt corresponding to the cell 61*c66ec88fSEmmanuel Vadot position. Allowed values are 4 - 127. Mapping for 62*c66ec88fSEmmanuel Vadot interrupts 0 - 3 (combined interrupt sources) are 63*c66ec88fSEmmanuel Vadot ignored. 64*c66ec88fSEmmanuel Vadot 65*c66ec88fSEmmanuel Vadot Interrupt Specifier Definition 66*c66ec88fSEmmanuel Vadot ------------------------------ 67*c66ec88fSEmmanuel Vadot Single cell specifying the megamodule interrupt source (4-127). Note that 68*c66ec88fSEmmanuel Vadot interrupts mapped directly to the core with "ti,c64x+megamod-pic-mux" will 69*c66ec88fSEmmanuel Vadot use the core interrupt controller as their parent and the specifier will 70*c66ec88fSEmmanuel Vadot be the core priority level, not the megamodule interrupt number. 71*c66ec88fSEmmanuel Vadot 72*c66ec88fSEmmanuel Vadot Examples 73*c66ec88fSEmmanuel Vadot -------- 74*c66ec88fSEmmanuel Vadot megamod_pic: interrupt-controller@1800000 { 75*c66ec88fSEmmanuel Vadot compatible = "ti,c64x+megamod-pic"; 76*c66ec88fSEmmanuel Vadot interrupt-controller; 77*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 78*c66ec88fSEmmanuel Vadot reg = <0x1800000 0x1000>; 79*c66ec88fSEmmanuel Vadot interrupt-parent = <&core_pic>; 80*c66ec88fSEmmanuel Vadot interrupts = < 12 13 14 15 >; 81*c66ec88fSEmmanuel Vadot }; 82*c66ec88fSEmmanuel Vadot 83*c66ec88fSEmmanuel Vadot This is a minimal example where all individual interrupts go through a 84*c66ec88fSEmmanuel Vadot combiner. Combiner-0 is mapped to core interrupt 12, combiner-1 is mapped 85*c66ec88fSEmmanuel Vadot to interrupt 13, etc. 86*c66ec88fSEmmanuel Vadot 87*c66ec88fSEmmanuel Vadot 88*c66ec88fSEmmanuel Vadot megamod_pic: interrupt-controller@1800000 { 89*c66ec88fSEmmanuel Vadot compatible = "ti,c64x+megamod-pic"; 90*c66ec88fSEmmanuel Vadot interrupt-controller; 91*c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 92*c66ec88fSEmmanuel Vadot reg = <0x1800000 0x1000>; 93*c66ec88fSEmmanuel Vadot interrupt-parent = <&core_pic>; 94*c66ec88fSEmmanuel Vadot interrupts = < 12 13 14 15 >; 95*c66ec88fSEmmanuel Vadot ti,c64x+megamod-pic-mux = < 0 0 0 0 96*c66ec88fSEmmanuel Vadot 32 0 0 0 97*c66ec88fSEmmanuel Vadot 0 0 0 0 >; 98*c66ec88fSEmmanuel Vadot }; 99*c66ec88fSEmmanuel Vadot 100*c66ec88fSEmmanuel Vadot This the same as the first example except that megamodule interrupt 32 is 101*c66ec88fSEmmanuel Vadot mapped directly to core priority interrupt 8. The node using this interrupt 102*c66ec88fSEmmanuel Vadot must set the core controller as its interrupt parent and use 8 in the 103*c66ec88fSEmmanuel Vadot interrupt specifier value. 104