1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/ti,pruss-intc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI PRU-ICSS Local Interrupt Controller
8
9maintainers:
10  - Suman Anna <s-anna@ti.com>
11
12description: |
13  Each PRU-ICSS has a single interrupt controller instance that is common
14  to all the PRU cores. Most interrupt controllers can route 64 input events
15  which are then mapped to 10 possible output interrupts through two levels
16  of mapping. The input events can be triggered by either the PRUs and/or
17  various other PRUSS internal and external peripherals. The first 2 output
18  interrupts (0, 1) are fed exclusively to the internal PRU cores, with the
19  remaining 8 (2 through 9) connected to external interrupt controllers
20  including the MPU and/or other PRUSS instances, DSPs or devices.
21
22  The property "ti,irqs-reserved" is used for denoting the connection
23  differences on the output interrupts 2 through 9. If this property is not
24  defined, it implies that all the PRUSS INTC output interrupts 2 through 9
25  (host_intr0 through host_intr7) are connected exclusively to the Arm interrupt
26  controller.
27
28  The K3 family of SoCs can handle 160 input events that can be mapped to 20
29  different possible output interrupts. The additional output interrupts (10
30  through 19) are connected to new sub-modules within the ICSSG instances.
31
32  This interrupt-controller node should be defined as a child node of the
33  corresponding PRUSS node. The node should be named "interrupt-controller".
34
35properties:
36  compatible:
37    enum:
38      - ti,pruss-intc
39      - ti,icssg-intc
40    description: |
41      Use "ti,pruss-intc" for OMAP-L13x/AM18x/DA850 SoCs,
42                              AM335x family of SoCs,
43                              AM437x family of SoCs,
44                              AM57xx family of SoCs
45                              66AK2G family of SoCs
46      Use "ti,icssg-intc" for K3 AM65x & J721E family of SoCs
47
48  reg:
49    maxItems: 1
50
51  interrupts:
52    minItems: 1
53    maxItems: 8
54    description: |
55      All the interrupts generated towards the main host processor in the SoC.
56      A shared interrupt can be skipped if the desired destination and usage is
57      by a different processor/device.
58
59  interrupt-names:
60    minItems: 1
61    maxItems: 8
62    items:
63      pattern: host_intr[0-7]
64    description: |
65      Should use one of the above names for each valid host event interrupt
66      connected to Arm interrupt controller, the name should match the
67      corresponding host event interrupt number.
68
69  interrupt-controller: true
70
71  "#interrupt-cells":
72    const: 3
73    description: |
74      Client users shall use the PRU System event number (the interrupt source
75      that the client is interested in) [cell 1], PRU channel [cell 2] and PRU
76      host_event (target) [cell 3] as the value of the interrupts property in
77      their node.  The system events can be mapped to some output host
78      interrupts through 2 levels of many-to-one mapping i.e. events to channel
79      mapping and channels to host interrupts so through this property entire
80      mapping is provided.
81
82  ti,irqs-reserved:
83    $ref: /schemas/types.yaml#definitions/uint8
84    description: |
85      Bitmask of host interrupts between 0 and 7 (corresponding to PRUSS INTC
86      output interrupts 2 through 9) that are not connected to the Arm interrupt
87      controller or are shared and used by other devices or processors in the
88      SoC. Define this property when any of 8 interrupts should not be handled
89      by Arm interrupt controller.
90        Eg: - AM437x and 66AK2G SoCs do not have "host_intr5" interrupt
91              connected to MPU
92            - AM65x and J721E SoCs have "host_intr5", "host_intr6" and
93              "host_intr7" interrupts connected to MPU, and other ICSSG
94              instances.
95
96required:
97  - compatible
98  - reg
99  - interrupts
100  - interrupt-names
101  - interrupt-controller
102  - "#interrupt-cells"
103
104additionalProperties: false
105
106examples:
107  - |
108    /* AM33xx PRU-ICSS */
109    pruss: pruss@0 {
110        compatible = "ti,am3356-pruss";
111        reg = <0x0 0x80000>;
112        #address-cells = <1>;
113        #size-cells = <1>;
114        ranges;
115
116        pruss_intc: interrupt-controller@20000 {
117            compatible = "ti,pruss-intc";
118            reg = <0x20000 0x2000>;
119            interrupts = <20 21 22 23 24 25 26 27>;
120            interrupt-names = "host_intr0", "host_intr1",
121                              "host_intr2", "host_intr3",
122                              "host_intr4", "host_intr5",
123                              "host_intr6", "host_intr7";
124            interrupt-controller;
125            #interrupt-cells = <3>;
126        };
127    };
128
129  - |
130
131    /* AM4376 PRU-ICSS */
132    #include <dt-bindings/interrupt-controller/arm-gic.h>
133    pruss@0 {
134        compatible = "ti,am4376-pruss";
135        reg = <0x0 0x40000>;
136        #address-cells = <1>;
137        #size-cells = <1>;
138        ranges;
139
140        interrupt-controller@20000 {
141            compatible = "ti,pruss-intc";
142            reg = <0x20000 0x2000>;
143            interrupt-controller;
144            #interrupt-cells = <3>;
145            interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
146                   <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
147                   <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
148                   <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
149                   <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>,
150                   <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>,
151                   <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
152            interrupt-names = "host_intr0", "host_intr1",
153                              "host_intr2", "host_intr3",
154                              "host_intr4",
155                              "host_intr6", "host_intr7";
156            ti,irqs-reserved = /bits/ 8 <0x20>; /* BIT(5) */
157        };
158    };
159