1* QCOM IOMMU v1 Implementation
2
3Qualcomm "B" family devices which are not compatible with arm-smmu have
4a similar looking IOMMU but without access to the global register space,
5and optionally requiring additional configuration to route context irqs
6to non-secure vs secure interrupt line.
7
8** Required properties:
9
10- compatible       : Should be one of:
11
12                        "qcom,msm8916-iommu"
13                        "qcom,msm8953-iommu"
14
15                     Followed by "qcom,msm-iommu-v1".
16
17- clock-names      : Should be a pair of "iface" (required for IOMMUs
18                     register group access) and "bus" (required for
19                     the IOMMUs underlying bus access).
20
21- clocks           : Phandles for respective clocks described by
22                     clock-names.
23
24- #address-cells   : must be 1.
25
26- #size-cells      : must be 1.
27
28- #iommu-cells     : Must be 1.  Index identifies the context-bank #.
29
30- ranges           : Base address and size of the iommu context banks.
31
32- qcom,iommu-secure-id  : secure-id.
33
34- List of sub-nodes, one per translation context bank.  Each sub-node
35  has the following required properties:
36
37  - compatible     : Should be one of:
38        - "qcom,msm-iommu-v1-ns"  : non-secure context bank
39        - "qcom,msm-iommu-v1-sec" : secure context bank
40  - reg            : Base address and size of context bank within the iommu
41  - interrupts     : The context fault irq.
42
43** Optional properties:
44
45- reg              : Base address and size of the SMMU local base, should
46                     be only specified if the iommu requires configuration
47                     for routing of context bank irq's to secure vs non-
48                     secure lines.  (Ie. if the iommu contains secure
49                     context banks)
50
51
52** Examples:
53
54	apps_iommu: iommu@1e20000 {
55		#address-cells = <1>;
56		#size-cells = <1>;
57		#iommu-cells = <1>;
58		compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
59		ranges = <0 0x1e20000 0x40000>;
60		reg = <0x1ef0000 0x3000>;
61		clocks = <&gcc GCC_SMMU_CFG_CLK>,
62			 <&gcc GCC_APSS_TCU_CLK>;
63		clock-names = "iface", "bus";
64		qcom,iommu-secure-id = <17>;
65
66		// mdp_0:
67		iommu-ctx@4000 {
68			compatible = "qcom,msm-iommu-v1-ns";
69			reg = <0x4000 0x1000>;
70			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
71		};
72
73		// venus_ns:
74		iommu-ctx@5000 {
75			compatible = "qcom,msm-iommu-v1-sec";
76			reg = <0x5000 0x1000>;
77			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
78		};
79	};
80
81	gpu_iommu: iommu@1f08000 {
82		#address-cells = <1>;
83		#size-cells = <1>;
84		#iommu-cells = <1>;
85		compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
86		ranges = <0 0x1f08000 0x10000>;
87		clocks = <&gcc GCC_SMMU_CFG_CLK>,
88			 <&gcc GCC_GFX_TCU_CLK>;
89		clock-names = "iface", "bus";
90		qcom,iommu-secure-id = <18>;
91
92		// gfx3d_user:
93		iommu-ctx@1000 {
94			compatible = "qcom,msm-iommu-v1-ns";
95			reg = <0x1000 0x1000>;
96			interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
97		};
98
99		// gfx3d_priv:
100		iommu-ctx@2000 {
101			compatible = "qcom,msm-iommu-v1-ns";
102			reg = <0x2000 0x1000>;
103			interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
104		};
105	};
106
107	...
108
109	venus: video-codec@1d00000 {
110		...
111		iommus = <&apps_iommu 5>;
112	};
113
114	mdp: mdp@1a01000 {
115		...
116		iommus = <&apps_iommu 4>;
117	};
118
119	gpu@1c00000 {
120		...
121		iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
122	};
123