1*c66ec88fSEmmanuel VadotFreescale i.MX Media Video Device 2*c66ec88fSEmmanuel Vadot================================= 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotVideo Media Controller node 5*c66ec88fSEmmanuel Vadot--------------------------- 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotThis is the media controller node for video capture support. It is a 8*c66ec88fSEmmanuel Vadotvirtual device that lists the camera serial interface nodes that the 9*c66ec88fSEmmanuel Vadotmedia device will control. 10*c66ec88fSEmmanuel Vadot 11*c66ec88fSEmmanuel VadotRequired properties: 12*c66ec88fSEmmanuel Vadot- compatible : "fsl,imx-capture-subsystem"; 13*c66ec88fSEmmanuel Vadot- ports : Should contain a list of phandles pointing to camera 14*c66ec88fSEmmanuel Vadot sensor interface ports of IPU devices 15*c66ec88fSEmmanuel Vadot 16*c66ec88fSEmmanuel Vadotexample: 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel Vadotcapture-subsystem { 19*c66ec88fSEmmanuel Vadot compatible = "fsl,imx-capture-subsystem"; 20*c66ec88fSEmmanuel Vadot ports = <&ipu1_csi0>, <&ipu1_csi1>; 21*c66ec88fSEmmanuel Vadot}; 22*c66ec88fSEmmanuel Vadot 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadotmipi_csi2 node 25*c66ec88fSEmmanuel Vadot-------------- 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel VadotThis is the device node for the MIPI CSI-2 Receiver core in the i.MX 28*c66ec88fSEmmanuel VadotSoC. This is a Synopsys Designware MIPI CSI-2 host controller core 29*c66ec88fSEmmanuel Vadotcombined with a D-PHY core mixed into the same register block. In 30*c66ec88fSEmmanuel Vadotaddition this device consists of an i.MX-specific "CSI2IPU gasket" 31*c66ec88fSEmmanuel Vadotglue logic, also controlled from the same register block. The CSI2IPU 32*c66ec88fSEmmanuel Vadotgasket demultiplexes the four virtual channel streams from the host 33*c66ec88fSEmmanuel Vadotcontroller's 32-bit output image bus onto four 16-bit parallel busses 34*c66ec88fSEmmanuel Vadotto the i.MX IPU CSIs. 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel VadotRequired properties: 37*c66ec88fSEmmanuel Vadot- compatible : "fsl,imx6-mipi-csi2"; 38*c66ec88fSEmmanuel Vadot- reg : physical base address and length of the register set; 39*c66ec88fSEmmanuel Vadot- clocks : the MIPI CSI-2 receiver requires three clocks: hsi_tx 40*c66ec88fSEmmanuel Vadot (the D-PHY clock), video_27m (D-PHY PLL reference 41*c66ec88fSEmmanuel Vadot clock), and eim_podf; 42*c66ec88fSEmmanuel Vadot- clock-names : must contain "dphy", "ref", "pix"; 43*c66ec88fSEmmanuel Vadot- port@* : five port nodes must exist, containing endpoints 44*c66ec88fSEmmanuel Vadot connecting to the source and sink devices according to 45*c66ec88fSEmmanuel Vadot of_graph bindings. The first port is an input port, 46*c66ec88fSEmmanuel Vadot connecting with a MIPI CSI-2 source, and ports 1 47*c66ec88fSEmmanuel Vadot through 4 are output ports connecting with parallel 48*c66ec88fSEmmanuel Vadot bus sink endpoint nodes and correspond to the four 49*c66ec88fSEmmanuel Vadot MIPI CSI-2 virtual channel outputs. 50*c66ec88fSEmmanuel Vadot 51*c66ec88fSEmmanuel VadotOptional properties: 52*c66ec88fSEmmanuel Vadot- interrupts : must contain two level-triggered interrupts, 53*c66ec88fSEmmanuel Vadot in order: 100 and 101; 54