1c9ccf3a3SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2c9ccf3a3SEmmanuel Vadot 3c9ccf3a3SEmmanuel Vadot%YAML 1.2 4c9ccf3a3SEmmanuel Vadot--- 5fac71e4eSEmmanuel Vadot$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml# 6fac71e4eSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 7c9ccf3a3SEmmanuel Vadot 8c9ccf3a3SEmmanuel Vadottitle: Mediatek Video Decode Accelerator With Multi Hardware 9c9ccf3a3SEmmanuel Vadot 10c9ccf3a3SEmmanuel Vadotmaintainers: 11c9ccf3a3SEmmanuel Vadot - Yunfei Dong <yunfei.dong@mediatek.com> 12c9ccf3a3SEmmanuel Vadot 13c9ccf3a3SEmmanuel Vadotdescription: | 14c9ccf3a3SEmmanuel Vadot Mediatek Video Decode is the video decode hardware present in Mediatek 15c9ccf3a3SEmmanuel Vadot SoCs which supports high resolution decoding functionalities. Required 16c9ccf3a3SEmmanuel Vadot parent and child device node. 17c9ccf3a3SEmmanuel Vadot 18c9ccf3a3SEmmanuel Vadot About the Decoder Hardware Block Diagram, please check below: 19c9ccf3a3SEmmanuel Vadot 20b97ee269SEmmanuel Vadot +------------------------------------------------+-------------------------------------+ 21c9ccf3a3SEmmanuel Vadot | | | 22b97ee269SEmmanuel Vadot | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | 23b97ee269SEmmanuel Vadot | || || | || | 24b97ee269SEmmanuel Vadot +------------||-------------||-------------------+---------------------||--------------+ 25b97ee269SEmmanuel Vadot || lat || | core workqueue <parent> 26b97ee269SEmmanuel Vadot -------------||-------------||-------------------|---------------------||--------------- 27b97ee269SEmmanuel Vadot ||<------------||----------------HW index---------------->|| <child> 28b97ee269SEmmanuel Vadot \/ \/ \/ 29b97ee269SEmmanuel Vadot +-------------------------------------------------------------+ 30c9ccf3a3SEmmanuel Vadot | enable/disable | 31c9ccf3a3SEmmanuel Vadot | clk power irq iommu | 32c9ccf3a3SEmmanuel Vadot | (lat/lat soc/core0/core1) | 33b97ee269SEmmanuel Vadot +-------------------------------------------------------------+ 34c9ccf3a3SEmmanuel Vadot 35c9ccf3a3SEmmanuel Vadot As above, there are parent and child devices, child mean each hardware. The child device 36c9ccf3a3SEmmanuel Vadot controls the information of each hardware independent which include clk/power/irq. 37c9ccf3a3SEmmanuel Vadot 38c9ccf3a3SEmmanuel Vadot There are two workqueues in parent device: lat workqueue and core workqueue. They are used 39*aa1a8ff2SEmmanuel Vadot to lat and core hardware decoder. Lat workqueue need to get input bitstream and lat buffer, 40c9ccf3a3SEmmanuel Vadot then enable lat to decode, writing the result to lat buffer, dislabe hardware when lat decode 41c9ccf3a3SEmmanuel Vadot done. Core workqueue need to get lat buffer and output buffer, then enable core to decode, 42c9ccf3a3SEmmanuel Vadot writing the result to output buffer, disable hardware when core decode done. These two 43c9ccf3a3SEmmanuel Vadot hardwares will decode each frame cyclically. 44c9ccf3a3SEmmanuel Vadot 45c9ccf3a3SEmmanuel Vadot For the smi common may not the same for each hardware, can't combine all hardware in one node, 46c9ccf3a3SEmmanuel Vadot or leading to iommu fault when access dram data. 47c9ccf3a3SEmmanuel Vadot 48b97ee269SEmmanuel Vadot Lat soc is a hardware which is related with some larb(local arbiter) ports. For mt8195 49b97ee269SEmmanuel Vadot platform, there are some ports like RDMA, UFO in lat soc larb, need to enable its power and 50b97ee269SEmmanuel Vadot clock when lat start to work, don't have interrupt. 51b97ee269SEmmanuel Vadot 52b97ee269SEmmanuel Vadot mt8195: lat soc HW + lat HW + core HW 53b97ee269SEmmanuel Vadot mt8192: lat HW + core HW 54b97ee269SEmmanuel Vadot 55c9ccf3a3SEmmanuel Vadotproperties: 56c9ccf3a3SEmmanuel Vadot compatible: 57d5b0e70fSEmmanuel Vadot enum: 58d5b0e70fSEmmanuel Vadot - mediatek,mt8192-vcodec-dec 59d5b0e70fSEmmanuel Vadot - mediatek,mt8186-vcodec-dec 607ef62cebSEmmanuel Vadot - mediatek,mt8188-vcodec-dec 61b97ee269SEmmanuel Vadot - mediatek,mt8195-vcodec-dec 62c9ccf3a3SEmmanuel Vadot 63c9ccf3a3SEmmanuel Vadot reg: 64fac71e4eSEmmanuel Vadot minItems: 1 65fac71e4eSEmmanuel Vadot items: 66fac71e4eSEmmanuel Vadot - description: VDEC_SYS register space 67fac71e4eSEmmanuel Vadot - description: VDEC_RACING_CTRL register space 68c9ccf3a3SEmmanuel Vadot 69c9ccf3a3SEmmanuel Vadot iommus: 70c9ccf3a3SEmmanuel Vadot minItems: 1 71c9ccf3a3SEmmanuel Vadot maxItems: 32 72c9ccf3a3SEmmanuel Vadot description: | 73c9ccf3a3SEmmanuel Vadot List of the hardware port in respective IOMMU block for current Socs. 74c9ccf3a3SEmmanuel Vadot Refer to bindings/iommu/mediatek,iommu.yaml. 75c9ccf3a3SEmmanuel Vadot 76c9ccf3a3SEmmanuel Vadot mediatek,scp: 77c9ccf3a3SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle 78c9ccf3a3SEmmanuel Vadot description: | 79c9ccf3a3SEmmanuel Vadot The node of system control processor (SCP), using 80c9ccf3a3SEmmanuel Vadot the remoteproc & rpmsg framework. 81c9ccf3a3SEmmanuel Vadot 82c9ccf3a3SEmmanuel Vadot "#address-cells": 83c9ccf3a3SEmmanuel Vadot const: 2 84c9ccf3a3SEmmanuel Vadot 85c9ccf3a3SEmmanuel Vadot "#size-cells": 86c9ccf3a3SEmmanuel Vadot const: 2 87c9ccf3a3SEmmanuel Vadot 88c9ccf3a3SEmmanuel Vadot ranges: true 89c9ccf3a3SEmmanuel Vadot 90c9ccf3a3SEmmanuel Vadot# Required child node: 91c9ccf3a3SEmmanuel VadotpatternProperties: 92fac71e4eSEmmanuel Vadot '^video-codec@[0-9a-f]+$': 93c9ccf3a3SEmmanuel Vadot type: object 94c9ccf3a3SEmmanuel Vadot 95c9ccf3a3SEmmanuel Vadot properties: 96c9ccf3a3SEmmanuel Vadot compatible: 97b97ee269SEmmanuel Vadot enum: 98fac71e4eSEmmanuel Vadot - mediatek,mtk-vcodec-core 99b97ee269SEmmanuel Vadot - mediatek,mtk-vcodec-lat 100b97ee269SEmmanuel Vadot - mediatek,mtk-vcodec-lat-soc 101c9ccf3a3SEmmanuel Vadot 102c9ccf3a3SEmmanuel Vadot reg: 103c9ccf3a3SEmmanuel Vadot maxItems: 1 104fac71e4eSEmmanuel Vadot description: VDEC_MISC register space 105c9ccf3a3SEmmanuel Vadot 106c9ccf3a3SEmmanuel Vadot interrupts: 107c9ccf3a3SEmmanuel Vadot maxItems: 1 108c9ccf3a3SEmmanuel Vadot 109c9ccf3a3SEmmanuel Vadot iommus: 110c9ccf3a3SEmmanuel Vadot minItems: 1 111c9ccf3a3SEmmanuel Vadot maxItems: 32 112c9ccf3a3SEmmanuel Vadot description: | 113c9ccf3a3SEmmanuel Vadot List of the hardware port in respective IOMMU block for current Socs. 114c9ccf3a3SEmmanuel Vadot Refer to bindings/iommu/mediatek,iommu.yaml. 115c9ccf3a3SEmmanuel Vadot 116c9ccf3a3SEmmanuel Vadot clocks: 117fac71e4eSEmmanuel Vadot minItems: 4 118c9ccf3a3SEmmanuel Vadot maxItems: 5 119c9ccf3a3SEmmanuel Vadot 120c9ccf3a3SEmmanuel Vadot clock-names: 121fac71e4eSEmmanuel Vadot minItems: 4 122fac71e4eSEmmanuel Vadot maxItems: 5 123c9ccf3a3SEmmanuel Vadot 124c9ccf3a3SEmmanuel Vadot assigned-clocks: 125c9ccf3a3SEmmanuel Vadot maxItems: 1 126c9ccf3a3SEmmanuel Vadot 127c9ccf3a3SEmmanuel Vadot assigned-clock-parents: 128c9ccf3a3SEmmanuel Vadot maxItems: 1 129c9ccf3a3SEmmanuel Vadot 130c9ccf3a3SEmmanuel Vadot power-domains: 131c9ccf3a3SEmmanuel Vadot maxItems: 1 132c9ccf3a3SEmmanuel Vadot 133c9ccf3a3SEmmanuel Vadot required: 134c9ccf3a3SEmmanuel Vadot - compatible 135c9ccf3a3SEmmanuel Vadot - reg 136c9ccf3a3SEmmanuel Vadot - iommus 137c9ccf3a3SEmmanuel Vadot - clocks 138c9ccf3a3SEmmanuel Vadot - clock-names 139c9ccf3a3SEmmanuel Vadot - assigned-clocks 140c9ccf3a3SEmmanuel Vadot - assigned-clock-parents 141c9ccf3a3SEmmanuel Vadot - power-domains 142c9ccf3a3SEmmanuel Vadot 143c9ccf3a3SEmmanuel Vadot additionalProperties: false 144c9ccf3a3SEmmanuel Vadot 145c9ccf3a3SEmmanuel Vadotrequired: 146c9ccf3a3SEmmanuel Vadot - compatible 147c9ccf3a3SEmmanuel Vadot - reg 148c9ccf3a3SEmmanuel Vadot - iommus 149c9ccf3a3SEmmanuel Vadot - mediatek,scp 150c9ccf3a3SEmmanuel Vadot - ranges 151c9ccf3a3SEmmanuel Vadot 152b97ee269SEmmanuel Vadotif: 153b97ee269SEmmanuel Vadot properties: 154b97ee269SEmmanuel Vadot compatible: 155b97ee269SEmmanuel Vadot contains: 156b97ee269SEmmanuel Vadot enum: 157fac71e4eSEmmanuel Vadot - mediatek,mtk-vcodec-core 158b97ee269SEmmanuel Vadot - mediatek,mtk-vcodec-lat 159b97ee269SEmmanuel Vadot 160b97ee269SEmmanuel Vadotthen: 161b97ee269SEmmanuel Vadot required: 162b97ee269SEmmanuel Vadot - interrupts 163b97ee269SEmmanuel Vadot 164fac71e4eSEmmanuel VadotallOf: 165fac71e4eSEmmanuel Vadot - if: 166fac71e4eSEmmanuel Vadot properties: 167fac71e4eSEmmanuel Vadot compatible: 168fac71e4eSEmmanuel Vadot contains: 169fac71e4eSEmmanuel Vadot enum: 170fac71e4eSEmmanuel Vadot - mediatek,mt8192-vcodec-dec 171fac71e4eSEmmanuel Vadot then: 172fac71e4eSEmmanuel Vadot properties: 173fac71e4eSEmmanuel Vadot clock-names: 174fac71e4eSEmmanuel Vadot items: 175fac71e4eSEmmanuel Vadot - const: sel 176fac71e4eSEmmanuel Vadot - const: soc-vdec 177fac71e4eSEmmanuel Vadot - const: soc-lat 178fac71e4eSEmmanuel Vadot - const: vdec 179fac71e4eSEmmanuel Vadot - const: top 180fac71e4eSEmmanuel Vadot 181fac71e4eSEmmanuel Vadot - if: 182fac71e4eSEmmanuel Vadot properties: 183fac71e4eSEmmanuel Vadot compatible: 184fac71e4eSEmmanuel Vadot contains: 185fac71e4eSEmmanuel Vadot enum: 186fac71e4eSEmmanuel Vadot - mediatek,mt8195-vcodec-dec 187fac71e4eSEmmanuel Vadot then: 188fac71e4eSEmmanuel Vadot properties: 189fac71e4eSEmmanuel Vadot clock-names: 190fac71e4eSEmmanuel Vadot items: 191fac71e4eSEmmanuel Vadot - const: sel 192fac71e4eSEmmanuel Vadot - const: vdec 193fac71e4eSEmmanuel Vadot - const: lat 194fac71e4eSEmmanuel Vadot - const: top 195fac71e4eSEmmanuel Vadot 196c9ccf3a3SEmmanuel VadotadditionalProperties: false 197c9ccf3a3SEmmanuel Vadot 198c9ccf3a3SEmmanuel Vadotexamples: 199c9ccf3a3SEmmanuel Vadot - | 200c9ccf3a3SEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 201c9ccf3a3SEmmanuel Vadot #include <dt-bindings/memory/mt8192-larb-port.h> 202c9ccf3a3SEmmanuel Vadot #include <dt-bindings/interrupt-controller/irq.h> 203c9ccf3a3SEmmanuel Vadot #include <dt-bindings/clock/mt8192-clk.h> 204c9ccf3a3SEmmanuel Vadot #include <dt-bindings/power/mt8192-power.h> 205c9ccf3a3SEmmanuel Vadot 206c9ccf3a3SEmmanuel Vadot bus@16000000 { 207c9ccf3a3SEmmanuel Vadot #address-cells = <2>; 208c9ccf3a3SEmmanuel Vadot #size-cells = <2>; 209c9ccf3a3SEmmanuel Vadot ranges = <0 0x16000000 0x16000000 0 0x40000>; 210c9ccf3a3SEmmanuel Vadot 211c9ccf3a3SEmmanuel Vadot video-codec@16000000 { 212c9ccf3a3SEmmanuel Vadot compatible = "mediatek,mt8192-vcodec-dec"; 213c9ccf3a3SEmmanuel Vadot mediatek,scp = <&scp>; 214c9ccf3a3SEmmanuel Vadot iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>; 215c9ccf3a3SEmmanuel Vadot #address-cells = <2>; 216c9ccf3a3SEmmanuel Vadot #size-cells = <2>; 217c9ccf3a3SEmmanuel Vadot ranges = <0 0 0 0x16000000 0 0x40000>; 218c9ccf3a3SEmmanuel Vadot reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ 219fac71e4eSEmmanuel Vadot video-codec@10000 { 220c9ccf3a3SEmmanuel Vadot compatible = "mediatek,mtk-vcodec-lat"; 221c9ccf3a3SEmmanuel Vadot reg = <0 0x10000 0 0x800>; 222c9ccf3a3SEmmanuel Vadot interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>; 223c9ccf3a3SEmmanuel Vadot iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>, 224c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>, 225c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>, 226c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>, 227c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>, 228c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, 229c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, 230c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; 231c9ccf3a3SEmmanuel Vadot clocks = <&topckgen CLK_TOP_VDEC_SEL>, 232c9ccf3a3SEmmanuel Vadot <&vdecsys_soc CLK_VDEC_SOC_VDEC>, 233c9ccf3a3SEmmanuel Vadot <&vdecsys_soc CLK_VDEC_SOC_LAT>, 234c9ccf3a3SEmmanuel Vadot <&vdecsys_soc CLK_VDEC_SOC_LARB1>, 235c9ccf3a3SEmmanuel Vadot <&topckgen CLK_TOP_MAINPLL_D4>; 236c9ccf3a3SEmmanuel Vadot clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 237c9ccf3a3SEmmanuel Vadot assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 238c9ccf3a3SEmmanuel Vadot assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 239c9ccf3a3SEmmanuel Vadot power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; 240c9ccf3a3SEmmanuel Vadot }; 241c9ccf3a3SEmmanuel Vadot 242fac71e4eSEmmanuel Vadot video-codec@25000 { 243c9ccf3a3SEmmanuel Vadot compatible = "mediatek,mtk-vcodec-core"; 244c9ccf3a3SEmmanuel Vadot reg = <0 0x25000 0 0x1000>; 245c9ccf3a3SEmmanuel Vadot interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>; 246c9ccf3a3SEmmanuel Vadot iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>, 247c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>, 248c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>, 249c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>, 250c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>, 251c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>, 252c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>, 253c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>, 254c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, 255c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, 256c9ccf3a3SEmmanuel Vadot <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; 257c9ccf3a3SEmmanuel Vadot clocks = <&topckgen CLK_TOP_VDEC_SEL>, 258c9ccf3a3SEmmanuel Vadot <&vdecsys CLK_VDEC_VDEC>, 259c9ccf3a3SEmmanuel Vadot <&vdecsys CLK_VDEC_LAT>, 260c9ccf3a3SEmmanuel Vadot <&vdecsys CLK_VDEC_LARB1>, 261c9ccf3a3SEmmanuel Vadot <&topckgen CLK_TOP_MAINPLL_D4>; 262c9ccf3a3SEmmanuel Vadot clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; 263c9ccf3a3SEmmanuel Vadot assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; 264c9ccf3a3SEmmanuel Vadot assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; 265c9ccf3a3SEmmanuel Vadot power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; 266c9ccf3a3SEmmanuel Vadot }; 267c9ccf3a3SEmmanuel Vadot }; 268c9ccf3a3SEmmanuel Vadot }; 269