1* Mediatek JPEG Decoder
2
3Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs
4
5Required properties:
6- compatible : must be one of the following string:
7	"mediatek,mt8173-jpgdec"
8	"mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec"
9	"mediatek,mt2701-jpgdec"
10- reg : physical base address of the jpeg decoder registers and length of
11  memory mapped region.
12- interrupts : interrupt number to the interrupt controller.
13- clocks: device clocks, see
14  Documentation/devicetree/bindings/clock/clock-bindings.txt for details.
15- clock-names: must contain "jpgdec-smi" and "jpgdec".
16- power-domains: a phandle to the power domain, see
17  Documentation/devicetree/bindings/power/power_domain.txt for details.
18- mediatek,larb: must contain the local arbiters in the current Socs, see
19  Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml
20  for details.
21- iommus: should point to the respective IOMMU block with master port as
22  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
23  for details.
24
25Example:
26	jpegdec: jpegdec@15004000 {
27		compatible = "mediatek,mt2701-jpgdec";
28		reg = <0 0x15004000 0 0x1000>;
29		interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
30		clocks =  <&imgsys CLK_IMG_JPGDEC_SMI>,
31			  <&imgsys CLK_IMG_JPGDEC>;
32		clock-names = "jpgdec-smi",
33			      "jpgdec";
34		power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
35		mediatek,larb = <&larb2>;
36		iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>,
37			 <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>;
38	};
39