1Mediatek Video Codec
2
3Mediatek Video Codec is the video codec hw present in Mediatek SoCs which
4supports high resolution encoding and decoding functionalities.
5
6Required properties:
7- compatible : must be one of the following string:
8  "mediatek,mt8173-vcodec-enc-vp8" for mt8173 vp8 encoder.
9  "mediatek,mt8173-vcodec-enc" for mt8173 avc encoder.
10  "mediatek,mt8183-vcodec-enc" for MT8183 encoder.
11  "mediatek,mt8173-vcodec-dec" for MT8173 decoder.
12  "mediatek,mt8192-vcodec-enc" for MT8192 encoder.
13  "mediatek,mt8183-vcodec-dec" for MT8183 decoder.
14  "mediatek,mt8195-vcodec-enc" for MT8195 encoder.
15- reg : Physical base address of the video codec registers and length of
16  memory mapped region.
17- interrupts : interrupt number to the cpu.
18- mediatek,larb : must contain the local arbiters in the current Socs.
19- clocks : list of clock specifiers, corresponding to entries in
20  the clock-names property.
21- clock-names: avc encoder must contain "venc_sel", vp8 encoder must
22  contain "venc_lt_sel", decoder must contain "vcodecpll", "univpll_d2",
23  "clk_cci400_sel", "vdec_sel", "vdecpll", "vencpll", "venc_lt_sel",
24  "vdec_bus_clk_src".
25- iommus : should point to the respective IOMMU block with master port as
26  argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
27  for details.
28- dma-ranges : describes the dma address range space that the codec hw access.
29One of the two following nodes:
30- mediatek,vpu : the node of the video processor unit, if using VPU.
31- mediatek,scp : the node of the SCP unit, if using SCP.
32
33
34Example:
35
36vcodec_dec: vcodec@16000000 {
37    compatible = "mediatek,mt8173-vcodec-dec";
38    reg = <0 0x16000000 0 0x100>,   /*VDEC_SYS*/
39          <0 0x16020000 0 0x1000>,  /*VDEC_MISC*/
40          <0 0x16021000 0 0x800>,   /*VDEC_LD*/
41          <0 0x16021800 0 0x800>,   /*VDEC_TOP*/
42          <0 0x16022000 0 0x1000>,  /*VDEC_CM*/
43          <0 0x16023000 0 0x1000>,  /*VDEC_AD*/
44          <0 0x16024000 0 0x1000>,  /*VDEC_AV*/
45          <0 0x16025000 0 0x1000>,  /*VDEC_PP*/
46          <0 0x16026800 0 0x800>,   /*VP8_VD*/
47          <0 0x16027000 0 0x800>,   /*VP6_VD*/
48          <0 0x16027800 0 0x800>,   /*VP8_VL*/
49          <0 0x16028400 0 0x400>;   /*VP9_VD*/
50    interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_LOW>;
51    mediatek,larb = <&larb1>;
52    iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>,
53             <&iommu M4U_PORT_HW_VDEC_PP_EXT>,
54             <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>,
55             <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>,
56             <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>,
57             <&iommu M4U_PORT_HW_VDEC_UFO_EXT>,
58             <&iommu M4U_PORT_HW_VDEC_VLD_EXT>,
59             <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>;
60    mediatek,vpu = <&vpu>;
61    power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>;
62    clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>,
63             <&topckgen CLK_TOP_UNIVPLL_D2>,
64             <&topckgen CLK_TOP_CCI400_SEL>,
65             <&topckgen CLK_TOP_VDEC_SEL>,
66             <&topckgen CLK_TOP_VCODECPLL>,
67             <&apmixedsys CLK_APMIXED_VENCPLL>,
68             <&topckgen CLK_TOP_VENC_LT_SEL>,
69             <&topckgen CLK_TOP_VCODECPLL_370P5>;
70    clock-names = "vcodecpll",
71                  "univpll_d2",
72                  "clk_cci400_sel",
73                  "vdec_sel",
74                  "vdecpll",
75                  "vencpll",
76                  "venc_lt_sel",
77                  "vdec_bus_clk_src";
78    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>,
79                      <&topckgen CLK_TOP_CCI400_SEL>,
80                      <&topckgen CLK_TOP_VDEC_SEL>,
81                      <&apmixedsys CLK_APMIXED_VCODECPLL>,
82                      <&apmixedsys CLK_APMIXED_VENCPLL>;
83    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>,
84                             <&topckgen CLK_TOP_UNIVPLL_D2>,
85                             <&topckgen CLK_TOP_VCODECPLL>;
86    assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>;
87  };
88
89vcodec_enc_avc: vcodec@18002000 {
90    compatible = "mediatek,mt8173-vcodec-enc";
91    reg = <0 0x18002000 0 0x1000>;
92    interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
93    iommus = <&iommu M4U_PORT_VENC_RCPU>,
94             <&iommu M4U_PORT_VENC_REC>,
95             <&iommu M4U_PORT_VENC_BSDMA>,
96             <&iommu M4U_PORT_VENC_SV_COMV>,
97             <&iommu M4U_PORT_VENC_RD_COMV>,
98             <&iommu M4U_PORT_VENC_CUR_LUMA>,
99             <&iommu M4U_PORT_VENC_CUR_CHROMA>,
100             <&iommu M4U_PORT_VENC_REF_LUMA>,
101             <&iommu M4U_PORT_VENC_REF_CHROMA>,
102             <&iommu M4U_PORT_VENC_NBM_RDMA>,
103             <&iommu M4U_PORT_VENC_NBM_WDMA>;
104    mediatek,larb = <&larb3>;
105    mediatek,vpu = <&vpu>;
106    clocks = <&topckgen CLK_TOP_VENC_SEL>;
107    clock-names = "venc_sel";
108    assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>;
109    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL>;
110  };
111
112vcodec_enc_vp8: vcodec@19002000 {
113    compatible = "mediatek,mt8173-vcodec-enc-vp8";
114    reg =  <0 0x19002000 0 0x1000>;	/* VENC_LT_SYS */
115    interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
116    iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
117             <&iommu M4U_PORT_VENC_REC_FRM_SET2>,
118             <&iommu M4U_PORT_VENC_BSDMA_SET2>,
119             <&iommu M4U_PORT_VENC_SV_COMA_SET2>,
120             <&iommu M4U_PORT_VENC_RD_COMA_SET2>,
121             <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>,
122             <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>,
123             <&iommu M4U_PORT_VENC_REF_LUMA_SET2>,
124             <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>;
125    mediatek,larb = <&larb5>;
126    mediatek,vpu = <&vpu>;
127    clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
128    clock-names = "venc_lt_sel";
129    assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>;
130    assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>;
131  };
132