1Renesas R-Car Gen3 Digital Radio Interface controller (DRIF)
2------------------------------------------------------------
3
4R-Car Gen3 DRIF is a SPI like receive only slave device. A general
5representation of DRIF interfacing with a master device is shown below.
6
7+---------------------+                +---------------------+
8|                     |-----SCK------->|CLK                  |
9|       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
10|                     |-----SD0------->|D0                   |
11|                     |-----SD1------->|D1                   |
12+---------------------+                +---------------------+
13
14As per datasheet, each DRIF channel (drifn) is made up of two internal
15channels (drifn0 & drifn1). These two internal channels share the common
16CLK & SYNC. Each internal channel has its own dedicated resources like
17irq, dma channels, address space & clock. This internal split is not
18visible to the external master device.
19
20The device tree model represents each internal channel as a separate node.
21The internal channels sharing the CLK & SYNC are tied together by their
22phandles using a property called "renesas,bonding". For the rest of
23the documentation, unless explicitly stated, the word channel implies an
24internal channel.
25
26When both internal channels are enabled they need to be managed together
27as one (i.e.) they cannot operate alone as independent devices. Out of the
28two, one of them needs to act as a primary device that accepts common
29properties of both the internal channels. This channel is identified by a
30property called "renesas,primary-bond".
31
32To summarize,
33   - When both the internal channels that are bonded together are enabled,
34     the zeroth channel is selected as primary-bond. This channels accepts
35     properties common to all the members of the bond.
36   - When only one of the bonded channels need to be enabled, the property
37     "renesas,bonding" or "renesas,primary-bond" will have no effect. That
38     enabled channel can act alone as any other independent device.
39
40Required properties of an internal channel:
41-------------------------------------------
42- compatible:	"renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC.
43		"renesas,r8a7796-drif" if DRIF controller is a part of R8A7796 SoC.
44		"renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device.
45
46		When compatible with the generic version, nodes must list the
47		SoC-specific version corresponding to the platform first
48		followed by the generic version.
49
50- reg: offset and length of that channel.
51- interrupts: associated with that channel.
52- clocks: phandle and clock specifier of that channel.
53- clock-names: clock input name string: "fck".
54- dmas: phandles to the DMA channels.
55- dma-names: names of the DMA channel: "rx".
56- renesas,bonding: phandle to the other channel.
57
58Optional properties of an internal channel:
59-------------------------------------------
60- power-domains: phandle to the respective power domain.
61
62Required properties of an internal channel when:
63	- It is the only enabled channel of the bond (or)
64	- If it acts as primary among enabled bonds
65--------------------------------------------------------
66- pinctrl-0: pin control group to be used for this channel.
67- pinctrl-names: must be "default".
68- renesas,primary-bond: empty property indicating the channel acts as primary
69			among the bonded channels.
70- port: child port node corresponding to the data input, in accordance with
71	the video interface bindings defined in
72	Documentation/devicetree/bindings/media/video-interfaces.txt. The port
73	node must contain at least one endpoint.
74
75Optional endpoint property:
76---------------------------
77- sync-active: Indicates sync signal polarity, 0/1 for low/high respectively.
78	       This property maps to SYNCAC bit in the hardware manual. The
79	       default is 1 (active high).
80
81Example:
82--------
83
84(1) Both internal channels enabled:
85-----------------------------------
86
87When interfacing with a third party tuner device with two data pins as shown
88below.
89
90+---------------------+                +---------------------+
91|                     |-----SCK------->|CLK                  |
92|       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
93|                     |-----SD0------->|D0                   |
94|                     |-----SD1------->|D1                   |
95+---------------------+                +---------------------+
96
97	drif00: rif@e6f40000 {
98		compatible = "renesas,r8a7795-drif",
99			     "renesas,rcar-gen3-drif";
100		reg = <0 0xe6f40000 0 0x64>;
101		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
102		clocks = <&cpg CPG_MOD 515>;
103		clock-names = "fck";
104		dmas = <&dmac1 0x20>, <&dmac2 0x20>;
105		dma-names = "rx", "rx";
106		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
107		renesas,bonding = <&drif01>;
108		renesas,primary-bond;
109		pinctrl-0 = <&drif0_pins>;
110		pinctrl-names = "default";
111		port {
112			drif0_ep: endpoint {
113			     remote-endpoint = <&tuner_ep>;
114			};
115		};
116	};
117
118	drif01: rif@e6f50000 {
119		compatible = "renesas,r8a7795-drif",
120			     "renesas,rcar-gen3-drif";
121		reg = <0 0xe6f50000 0 0x64>;
122		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
123		clocks = <&cpg CPG_MOD 514>;
124		clock-names = "fck";
125		dmas = <&dmac1 0x22>, <&dmac2 0x22>;
126		dma-names = "rx", "rx";
127		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
128		renesas,bonding = <&drif00>;
129	};
130
131
132(2) Internal channel 1 alone is enabled:
133----------------------------------------
134
135When interfacing with a third party tuner device with one data pin as shown
136below.
137
138+---------------------+                +---------------------+
139|                     |-----SCK------->|CLK                  |
140|       Master        |-----SS-------->|SYNC  DRIFn (slave)  |
141|                     |                |D0 (unused)          |
142|                     |-----SD-------->|D1                   |
143+---------------------+                +---------------------+
144
145	drif00: rif@e6f40000 {
146		compatible = "renesas,r8a7795-drif",
147			     "renesas,rcar-gen3-drif";
148		reg = <0 0xe6f40000 0 0x64>;
149		interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
150		clocks = <&cpg CPG_MOD 515>;
151		clock-names = "fck";
152		dmas = <&dmac1 0x20>, <&dmac2 0x20>;
153		dma-names = "rx", "rx";
154		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
155		renesas,bonding = <&drif01>;
156	};
157
158	drif01: rif@e6f50000 {
159		compatible = "renesas,r8a7795-drif",
160			     "renesas,rcar-gen3-drif";
161		reg = <0 0xe6f50000 0 0x64>;
162		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
163		clocks = <&cpg CPG_MOD 514>;
164		clock-names = "fck";
165		dmas = <&dmac1 0x22>, <&dmac2 0x22>;
166		dma-names = "rx", "rx";
167		power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;
168		renesas,bonding = <&drif00>;
169		pinctrl-0 = <&drif0_pins>;
170		pinctrl-names = "default";
171		port {
172			drif0_ep: endpoint {
173			     remote-endpoint = <&tuner_ep>;
174			     sync-active = <0>;
175			};
176		};
177	};
178