1*8bab661aSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*8bab661aSEmmanuel Vadot%YAML 1.2 3*8bab661aSEmmanuel Vadot--- 4*8bab661aSEmmanuel Vadot$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml# 5*8bab661aSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8bab661aSEmmanuel Vadot 7*8bab661aSEmmanuel Vadottitle: LPDDR channel with chip/rank topology description 8*8bab661aSEmmanuel Vadot 9*8bab661aSEmmanuel Vadotdescription: 10*8bab661aSEmmanuel Vadot An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS, 11*8bab661aSEmmanuel Vadot CK, etc.) that connect one or more LPDDR chips to a host system. The main 12*8bab661aSEmmanuel Vadot purpose of this node is to overall LPDDR topology of the system, including the 13*8bab661aSEmmanuel Vadot amount of individual LPDDR chips and the ranks per chip. 14*8bab661aSEmmanuel Vadot 15*8bab661aSEmmanuel Vadotmaintainers: 16*8bab661aSEmmanuel Vadot - Julius Werner <jwerner@chromium.org> 17*8bab661aSEmmanuel Vadot 18*8bab661aSEmmanuel Vadotproperties: 19*8bab661aSEmmanuel Vadot compatible: 20*8bab661aSEmmanuel Vadot enum: 21*8bab661aSEmmanuel Vadot - jedec,lpddr2-channel 22*8bab661aSEmmanuel Vadot - jedec,lpddr3-channel 23*8bab661aSEmmanuel Vadot - jedec,lpddr4-channel 24*8bab661aSEmmanuel Vadot - jedec,lpddr5-channel 25*8bab661aSEmmanuel Vadot 26*8bab661aSEmmanuel Vadot io-width: 27*8bab661aSEmmanuel Vadot description: 28*8bab661aSEmmanuel Vadot The number of DQ pins in the channel. If this number is different 29*8bab661aSEmmanuel Vadot from (a multiple of) the io-width of the LPDDR chip, that means that 30*8bab661aSEmmanuel Vadot multiple instances of that type of chip are wired in parallel on this 31*8bab661aSEmmanuel Vadot channel (with the channel's DQ pins split up between the different 32*8bab661aSEmmanuel Vadot chips, and the CA, CS, etc. pins of the different chips all shorted 33*8bab661aSEmmanuel Vadot together). This means that the total physical memory controlled by a 34*8bab661aSEmmanuel Vadot channel is equal to the sum of the densities of each rank on the 35*8bab661aSEmmanuel Vadot connected LPDDR chip, times the io-width of the channel divided by 36*8bab661aSEmmanuel Vadot the io-width of the LPDDR chip. 37*8bab661aSEmmanuel Vadot enum: 38*8bab661aSEmmanuel Vadot - 8 39*8bab661aSEmmanuel Vadot - 16 40*8bab661aSEmmanuel Vadot - 32 41*8bab661aSEmmanuel Vadot - 64 42*8bab661aSEmmanuel Vadot - 128 43*8bab661aSEmmanuel Vadot 44*8bab661aSEmmanuel Vadot "#address-cells": 45*8bab661aSEmmanuel Vadot const: 1 46*8bab661aSEmmanuel Vadot 47*8bab661aSEmmanuel Vadot "#size-cells": 48*8bab661aSEmmanuel Vadot const: 0 49*8bab661aSEmmanuel Vadot 50*8bab661aSEmmanuel VadotpatternProperties: 51*8bab661aSEmmanuel Vadot "^rank@[0-9]+$": 52*8bab661aSEmmanuel Vadot type: object 53*8bab661aSEmmanuel Vadot description: 54*8bab661aSEmmanuel Vadot Each physical LPDDR chip may have one or more ranks. Ranks are 55*8bab661aSEmmanuel Vadot internal but fully independent sub-units of the chip. Each LPDDR bus 56*8bab661aSEmmanuel Vadot transaction on the channel targets exactly one rank, based on the 57*8bab661aSEmmanuel Vadot state of the CS pins. Different ranks may have different densities and 58*8bab661aSEmmanuel Vadot timing requirements. 59*8bab661aSEmmanuel Vadot required: 60*8bab661aSEmmanuel Vadot - reg 61*8bab661aSEmmanuel Vadot 62*8bab661aSEmmanuel VadotallOf: 63*8bab661aSEmmanuel Vadot - if: 64*8bab661aSEmmanuel Vadot properties: 65*8bab661aSEmmanuel Vadot compatible: 66*8bab661aSEmmanuel Vadot contains: 67*8bab661aSEmmanuel Vadot const: jedec,lpddr2-channel 68*8bab661aSEmmanuel Vadot then: 69*8bab661aSEmmanuel Vadot patternProperties: 70*8bab661aSEmmanuel Vadot "^rank@[0-9]+$": 71*8bab661aSEmmanuel Vadot $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml# 72*8bab661aSEmmanuel Vadot - if: 73*8bab661aSEmmanuel Vadot properties: 74*8bab661aSEmmanuel Vadot compatible: 75*8bab661aSEmmanuel Vadot contains: 76*8bab661aSEmmanuel Vadot const: jedec,lpddr3-channel 77*8bab661aSEmmanuel Vadot then: 78*8bab661aSEmmanuel Vadot patternProperties: 79*8bab661aSEmmanuel Vadot "^rank@[0-9]+$": 80*8bab661aSEmmanuel Vadot $ref: /schemas/memory-controllers/ddr/jedec,lpddr3.yaml# 81*8bab661aSEmmanuel Vadot - if: 82*8bab661aSEmmanuel Vadot properties: 83*8bab661aSEmmanuel Vadot compatible: 84*8bab661aSEmmanuel Vadot contains: 85*8bab661aSEmmanuel Vadot const: jedec,lpddr4-channel 86*8bab661aSEmmanuel Vadot then: 87*8bab661aSEmmanuel Vadot patternProperties: 88*8bab661aSEmmanuel Vadot "^rank@[0-9]+$": 89*8bab661aSEmmanuel Vadot $ref: /schemas/memory-controllers/ddr/jedec,lpddr4.yaml# 90*8bab661aSEmmanuel Vadot - if: 91*8bab661aSEmmanuel Vadot properties: 92*8bab661aSEmmanuel Vadot compatible: 93*8bab661aSEmmanuel Vadot contains: 94*8bab661aSEmmanuel Vadot const: jedec,lpddr5-channel 95*8bab661aSEmmanuel Vadot then: 96*8bab661aSEmmanuel Vadot patternProperties: 97*8bab661aSEmmanuel Vadot "^rank@[0-9]+$": 98*8bab661aSEmmanuel Vadot $ref: /schemas/memory-controllers/ddr/jedec,lpddr5.yaml# 99*8bab661aSEmmanuel Vadot 100*8bab661aSEmmanuel Vadotrequired: 101*8bab661aSEmmanuel Vadot - compatible 102*8bab661aSEmmanuel Vadot - io-width 103*8bab661aSEmmanuel Vadot - "#address-cells" 104*8bab661aSEmmanuel Vadot - "#size-cells" 105*8bab661aSEmmanuel Vadot 106*8bab661aSEmmanuel VadotadditionalProperties: false 107*8bab661aSEmmanuel Vadot 108*8bab661aSEmmanuel Vadotexamples: 109*8bab661aSEmmanuel Vadot - | 110*8bab661aSEmmanuel Vadot lpddr-channel0 { 111*8bab661aSEmmanuel Vadot #address-cells = <1>; 112*8bab661aSEmmanuel Vadot #size-cells = <0>; 113*8bab661aSEmmanuel Vadot compatible = "jedec,lpddr3-channel"; 114*8bab661aSEmmanuel Vadot io-width = <32>; 115*8bab661aSEmmanuel Vadot 116*8bab661aSEmmanuel Vadot rank@0 { 117*8bab661aSEmmanuel Vadot compatible = "lpddr3-ff,0100", "jedec,lpddr3"; 118*8bab661aSEmmanuel Vadot reg = <0>; 119*8bab661aSEmmanuel Vadot density = <8192>; 120*8bab661aSEmmanuel Vadot io-width = <16>; 121*8bab661aSEmmanuel Vadot revision-id = <1 0>; 122*8bab661aSEmmanuel Vadot }; 123*8bab661aSEmmanuel Vadot }; 124*8bab661aSEmmanuel Vadot 125*8bab661aSEmmanuel Vadot lpddr-channel1 { 126*8bab661aSEmmanuel Vadot #address-cells = <1>; 127*8bab661aSEmmanuel Vadot #size-cells = <0>; 128*8bab661aSEmmanuel Vadot compatible = "jedec,lpddr4-channel"; 129*8bab661aSEmmanuel Vadot io-width = <32>; 130*8bab661aSEmmanuel Vadot 131*8bab661aSEmmanuel Vadot rank@0 { 132*8bab661aSEmmanuel Vadot compatible = "lpddr4-05,0301", "jedec,lpddr4"; 133*8bab661aSEmmanuel Vadot reg = <0>; 134*8bab661aSEmmanuel Vadot density = <4096>; 135*8bab661aSEmmanuel Vadot io-width = <32>; 136*8bab661aSEmmanuel Vadot revision-id = <3 1>; 137*8bab661aSEmmanuel Vadot }; 138*8bab661aSEmmanuel Vadot 139*8bab661aSEmmanuel Vadot rank@1 { 140*8bab661aSEmmanuel Vadot compatible = "lpddr4-05,0301", "jedec,lpddr4"; 141*8bab661aSEmmanuel Vadot reg = <1>; 142*8bab661aSEmmanuel Vadot density = <2048>; 143*8bab661aSEmmanuel Vadot io-width = <32>; 144*8bab661aSEmmanuel Vadot revision-id = <3 1>; 145*8bab661aSEmmanuel Vadot }; 146*8bab661aSEmmanuel Vadot }; 147