1# SPDX-License-Identifier: (GPL-2.0)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra30 SoC External Memory Controller
8
9maintainers:
10  - Dmitry Osipenko <digetx@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Thierry Reding <thierry.reding@gmail.com>
13
14description: |
15  The EMC interfaces with the off-chip SDRAM to service the request stream
16  sent from Memory Controller. The EMC also has various performance-affecting
17  settings beyond the obvious SDRAM configuration parameters and initialization
18  settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
19  LPDDR3, and DDR3.
20
21properties:
22  compatible:
23    const: nvidia,tegra30-emc
24
25  reg:
26    maxItems: 1
27
28  clocks:
29    maxItems: 1
30
31  interrupts:
32    maxItems: 1
33
34  "#interconnect-cells":
35    const: 0
36
37  nvidia,memory-controller:
38    $ref: /schemas/types.yaml#/definitions/phandle
39    description:
40      Phandle of the Memory Controller node.
41
42  power-domains:
43    maxItems: 1
44    description:
45      Phandle of the SoC "core" power domain.
46
47  operating-points-v2:
48    description:
49      Should contain freqs and voltages and opp-supported-hw property, which
50      is a bitfield indicating SoC speedo ID mask.
51
52patternProperties:
53  "^emc-timings-[0-9]+$":
54    type: object
55    properties:
56      nvidia,ram-code:
57        $ref: /schemas/types.yaml#/definitions/uint32
58        description:
59          Value of RAM_CODE this timing set is used for.
60
61    patternProperties:
62      "^timing-[0-9]+$":
63        type: object
64        properties:
65          clock-frequency:
66            description:
67              Memory clock rate in Hz.
68            minimum: 1000000
69            maximum: 900000000
70
71          nvidia,emc-auto-cal-interval:
72            description:
73              Pad calibration interval in microseconds.
74            $ref: /schemas/types.yaml#/definitions/uint32
75            minimum: 0
76            maximum: 2097151
77
78          nvidia,emc-mode-1:
79            $ref: /schemas/types.yaml#/definitions/uint32
80            description:
81              Mode Register 1.
82
83          nvidia,emc-mode-2:
84            $ref: /schemas/types.yaml#/definitions/uint32
85            description:
86              Mode Register 2.
87
88          nvidia,emc-mode-reset:
89            $ref: /schemas/types.yaml#/definitions/uint32
90            description:
91              Mode Register 0.
92
93          nvidia,emc-zcal-cnt-long:
94            description:
95              Number of EMC clocks to wait before issuing any commands after
96              sending ZCAL_MRW_CMD.
97            $ref: /schemas/types.yaml#/definitions/uint32
98            minimum: 0
99            maximum: 1023
100
101          nvidia,emc-cfg-dyn-self-ref:
102            type: boolean
103            description:
104              Dynamic self-refresh enabled.
105
106          nvidia,emc-cfg-periodic-qrst:
107            type: boolean
108            description:
109              FBIO "read" FIFO periodic resetting enabled.
110
111          nvidia,emc-configuration:
112            description:
113              EMC timing characterization data. These are the registers
114              (see section "18.13.2 EMC Registers" in the TRM) whose values
115              need to be specified, according to the board documentation.
116            $ref: /schemas/types.yaml#/definitions/uint32-array
117            items:
118              - description: EMC_RC
119              - description: EMC_RFC
120              - description: EMC_RAS
121              - description: EMC_RP
122              - description: EMC_R2W
123              - description: EMC_W2R
124              - description: EMC_R2P
125              - description: EMC_W2P
126              - description: EMC_RD_RCD
127              - description: EMC_WR_RCD
128              - description: EMC_RRD
129              - description: EMC_REXT
130              - description: EMC_WEXT
131              - description: EMC_WDV
132              - description: EMC_QUSE
133              - description: EMC_QRST
134              - description: EMC_QSAFE
135              - description: EMC_RDV
136              - description: EMC_REFRESH
137              - description: EMC_BURST_REFRESH_NUM
138              - description: EMC_PRE_REFRESH_REQ_CNT
139              - description: EMC_PDEX2WR
140              - description: EMC_PDEX2RD
141              - description: EMC_PCHG2PDEN
142              - description: EMC_ACT2PDEN
143              - description: EMC_AR2PDEN
144              - description: EMC_RW2PDEN
145              - description: EMC_TXSR
146              - description: EMC_TXSRDLL
147              - description: EMC_TCKE
148              - description: EMC_TFAW
149              - description: EMC_TRPAB
150              - description: EMC_TCLKSTABLE
151              - description: EMC_TCLKSTOP
152              - description: EMC_TREFBW
153              - description: EMC_QUSE_EXTRA
154              - description: EMC_FBIO_CFG6
155              - description: EMC_ODT_WRITE
156              - description: EMC_ODT_READ
157              - description: EMC_FBIO_CFG5
158              - description: EMC_CFG_DIG_DLL
159              - description: EMC_CFG_DIG_DLL_PERIOD
160              - description: EMC_DLL_XFORM_DQS0
161              - description: EMC_DLL_XFORM_DQS1
162              - description: EMC_DLL_XFORM_DQS2
163              - description: EMC_DLL_XFORM_DQS3
164              - description: EMC_DLL_XFORM_DQS4
165              - description: EMC_DLL_XFORM_DQS5
166              - description: EMC_DLL_XFORM_DQS6
167              - description: EMC_DLL_XFORM_DQS7
168              - description: EMC_DLL_XFORM_QUSE0
169              - description: EMC_DLL_XFORM_QUSE1
170              - description: EMC_DLL_XFORM_QUSE2
171              - description: EMC_DLL_XFORM_QUSE3
172              - description: EMC_DLL_XFORM_QUSE4
173              - description: EMC_DLL_XFORM_QUSE5
174              - description: EMC_DLL_XFORM_QUSE6
175              - description: EMC_DLL_XFORM_QUSE7
176              - description: EMC_DLI_TRIM_TXDQS0
177              - description: EMC_DLI_TRIM_TXDQS1
178              - description: EMC_DLI_TRIM_TXDQS2
179              - description: EMC_DLI_TRIM_TXDQS3
180              - description: EMC_DLI_TRIM_TXDQS4
181              - description: EMC_DLI_TRIM_TXDQS5
182              - description: EMC_DLI_TRIM_TXDQS6
183              - description: EMC_DLI_TRIM_TXDQS7
184              - description: EMC_DLL_XFORM_DQ0
185              - description: EMC_DLL_XFORM_DQ1
186              - description: EMC_DLL_XFORM_DQ2
187              - description: EMC_DLL_XFORM_DQ3
188              - description: EMC_XM2CMDPADCTRL
189              - description: EMC_XM2DQSPADCTRL2
190              - description: EMC_XM2DQPADCTRL2
191              - description: EMC_XM2CLKPADCTRL
192              - description: EMC_XM2COMPPADCTRL
193              - description: EMC_XM2VTTGENPADCTRL
194              - description: EMC_XM2VTTGENPADCTRL2
195              - description: EMC_XM2QUSEPADCTRL
196              - description: EMC_XM2DQSPADCTRL3
197              - description: EMC_CTT_TERM_CTRL
198              - description: EMC_ZCAL_INTERVAL
199              - description: EMC_ZCAL_WAIT_CNT
200              - description: EMC_MRS_WAIT_CNT
201              - description: EMC_AUTO_CAL_CONFIG
202              - description: EMC_CTT
203              - description: EMC_CTT_DURATION
204              - description: EMC_DYN_SELF_REF_CONTROL
205              - description: EMC_FBIO_SPARE
206              - description: EMC_CFG_RSV
207
208        required:
209          - clock-frequency
210          - nvidia,emc-auto-cal-interval
211          - nvidia,emc-mode-1
212          - nvidia,emc-mode-2
213          - nvidia,emc-mode-reset
214          - nvidia,emc-zcal-cnt-long
215          - nvidia,emc-configuration
216
217        additionalProperties: false
218
219    required:
220      - nvidia,ram-code
221
222    additionalProperties: false
223
224required:
225  - compatible
226  - reg
227  - interrupts
228  - clocks
229  - nvidia,memory-controller
230  - "#interconnect-cells"
231  - operating-points-v2
232
233additionalProperties: false
234
235examples:
236  - |
237    external-memory-controller@7000f400 {
238        compatible = "nvidia,tegra30-emc";
239        reg = <0x7000f400 0x400>;
240        interrupts = <0 78 4>;
241        clocks = <&tegra_car 57>;
242
243        nvidia,memory-controller = <&mc>;
244        operating-points-v2 = <&dvfs_opp_table>;
245        power-domains = <&domain>;
246
247        #interconnect-cells = <0>;
248
249        emc-timings-1 {
250            nvidia,ram-code = <1>;
251
252            timing-667000000 {
253                clock-frequency = <667000000>;
254
255                nvidia,emc-auto-cal-interval = <0x001fffff>;
256                nvidia,emc-mode-1 = <0x80100002>;
257                nvidia,emc-mode-2 = <0x80200018>;
258                nvidia,emc-mode-reset = <0x80000b71>;
259                nvidia,emc-zcal-cnt-long = <0x00000040>;
260                nvidia,emc-cfg-periodic-qrst;
261
262                nvidia,emc-configuration = <
263                    0x00000020 /* EMC_RC */
264                    0x0000006a /* EMC_RFC */
265                    0x00000017 /* EMC_RAS */
266                    0x00000007 /* EMC_RP */
267                    0x00000005 /* EMC_R2W */
268                    0x0000000c /* EMC_W2R */
269                    0x00000003 /* EMC_R2P */
270                    0x00000011 /* EMC_W2P */
271                    0x00000007 /* EMC_RD_RCD */
272                    0x00000007 /* EMC_WR_RCD */
273                    0x00000002 /* EMC_RRD */
274                    0x00000001 /* EMC_REXT */
275                    0x00000000 /* EMC_WEXT */
276                    0x00000007 /* EMC_WDV */
277                    0x0000000a /* EMC_QUSE */
278                    0x00000009 /* EMC_QRST */
279                    0x0000000b /* EMC_QSAFE */
280                    0x00000011 /* EMC_RDV */
281                    0x00001412 /* EMC_REFRESH */
282                    0x00000000 /* EMC_BURST_REFRESH_NUM */
283                    0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */
284                    0x00000002 /* EMC_PDEX2WR */
285                    0x0000000e /* EMC_PDEX2RD */
286                    0x00000001 /* EMC_PCHG2PDEN */
287                    0x00000000 /* EMC_ACT2PDEN */
288                    0x0000000c /* EMC_AR2PDEN */
289                    0x00000016 /* EMC_RW2PDEN */
290                    0x00000072 /* EMC_TXSR */
291                    0x00000200 /* EMC_TXSRDLL */
292                    0x00000005 /* EMC_TCKE */
293                    0x00000015 /* EMC_TFAW */
294                    0x00000000 /* EMC_TRPAB */
295                    0x00000006 /* EMC_TCLKSTABLE */
296                    0x00000007 /* EMC_TCLKSTOP */
297                    0x00001453 /* EMC_TREFBW */
298                    0x0000000b /* EMC_QUSE_EXTRA */
299                    0x00000006 /* EMC_FBIO_CFG6 */
300                    0x00000000 /* EMC_ODT_WRITE */
301                    0x00000000 /* EMC_ODT_READ */
302                    0x00005088 /* EMC_FBIO_CFG5 */
303                    0xf00b0191 /* EMC_CFG_DIG_DLL */
304                    0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
305                    0x00000008 /* EMC_DLL_XFORM_DQS0 */
306                    0x00000008 /* EMC_DLL_XFORM_DQS1 */
307                    0x00000008 /* EMC_DLL_XFORM_DQS2 */
308                    0x00000008 /* EMC_DLL_XFORM_DQS3 */
309                    0x0000000a /* EMC_DLL_XFORM_DQS4 */
310                    0x0000000a /* EMC_DLL_XFORM_DQS5 */
311                    0x0000000a /* EMC_DLL_XFORM_DQS6 */
312                    0x0000000a /* EMC_DLL_XFORM_DQS7 */
313                    0x00018000 /* EMC_DLL_XFORM_QUSE0 */
314                    0x00018000 /* EMC_DLL_XFORM_QUSE1 */
315                    0x00018000 /* EMC_DLL_XFORM_QUSE2 */
316                    0x00018000 /* EMC_DLL_XFORM_QUSE3 */
317                    0x00000000 /* EMC_DLL_XFORM_QUSE4 */
318                    0x00000000 /* EMC_DLL_XFORM_QUSE5 */
319                    0x00000000 /* EMC_DLL_XFORM_QUSE6 */
320                    0x00000000 /* EMC_DLL_XFORM_QUSE7 */
321                    0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
322                    0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
323                    0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
324                    0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
325                    0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
326                    0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
327                    0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
328                    0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
329                    0x0000000a /* EMC_DLL_XFORM_DQ0 */
330                    0x0000000a /* EMC_DLL_XFORM_DQ1 */
331                    0x0000000a /* EMC_DLL_XFORM_DQ2 */
332                    0x0000000a /* EMC_DLL_XFORM_DQ3 */
333                    0x000002a0 /* EMC_XM2CMDPADCTRL */
334                    0x0800013d /* EMC_XM2DQSPADCTRL2 */
335                    0x22220000 /* EMC_XM2DQPADCTRL2 */
336                    0x77fff884 /* EMC_XM2CLKPADCTRL */
337                    0x01f1f501 /* EMC_XM2COMPPADCTRL */
338                    0x07077404 /* EMC_XM2VTTGENPADCTRL */
339                    0x54000000 /* EMC_XM2VTTGENPADCTRL2 */
340                    0x080001e8 /* EMC_XM2QUSEPADCTRL */
341                    0x0c000021 /* EMC_XM2DQSPADCTRL3 */
342                    0x00000802 /* EMC_CTT_TERM_CTRL */
343                    0x00020000 /* EMC_ZCAL_INTERVAL */
344                    0x00000100 /* EMC_ZCAL_WAIT_CNT */
345                    0x0155000c /* EMC_MRS_WAIT_CNT */
346                    0xa0f10000 /* EMC_AUTO_CAL_CONFIG */
347                    0x00000000 /* EMC_CTT */
348                    0x00000000 /* EMC_CTT_DURATION */
349                    0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */
350                    0xe8000000 /* EMC_FBIO_SPARE */
351                    0xff00ff49 /* EMC_CFG_RSV */
352                >;
353            };
354        };
355    };
356