1*8bab661aSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2*8bab661aSEmmanuel Vadot%YAML 1.2 3*8bab661aSEmmanuel Vadot--- 4*8bab661aSEmmanuel Vadot$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml# 5*8bab661aSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*8bab661aSEmmanuel Vadot 7*8bab661aSEmmanuel Vadottitle: Peripheral properties for ST FMC2 Controller 8*8bab661aSEmmanuel Vadot 9*8bab661aSEmmanuel Vadotmaintainers: 10*8bab661aSEmmanuel Vadot - Christophe Kerello <christophe.kerello@foss.st.com> 11*8bab661aSEmmanuel Vadot - Marek Vasut <marex@denx.de> 12*8bab661aSEmmanuel Vadot 13*8bab661aSEmmanuel Vadotproperties: 14*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-transaction-type: 15*8bab661aSEmmanuel Vadot description: | 16*8bab661aSEmmanuel Vadot Select one of the transactions type supported 17*8bab661aSEmmanuel Vadot 0: Asynchronous mode 1 SRAM/FRAM. 18*8bab661aSEmmanuel Vadot 1: Asynchronous mode 1 PSRAM. 19*8bab661aSEmmanuel Vadot 2: Asynchronous mode A SRAM/FRAM. 20*8bab661aSEmmanuel Vadot 3: Asynchronous mode A PSRAM. 21*8bab661aSEmmanuel Vadot 4: Asynchronous mode 2 NOR. 22*8bab661aSEmmanuel Vadot 5: Asynchronous mode B NOR. 23*8bab661aSEmmanuel Vadot 6: Asynchronous mode C NOR. 24*8bab661aSEmmanuel Vadot 7: Asynchronous mode D NOR. 25*8bab661aSEmmanuel Vadot 8: Synchronous read synchronous write PSRAM. 26*8bab661aSEmmanuel Vadot 9: Synchronous read asynchronous write PSRAM. 27*8bab661aSEmmanuel Vadot 10: Synchronous read synchronous write NOR. 28*8bab661aSEmmanuel Vadot 11: Synchronous read asynchronous write NOR. 29*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 30*8bab661aSEmmanuel Vadot minimum: 0 31*8bab661aSEmmanuel Vadot maximum: 11 32*8bab661aSEmmanuel Vadot 33*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-cclk-enable: 34*8bab661aSEmmanuel Vadot description: Continuous clock enable (first bank must be configured 35*8bab661aSEmmanuel Vadot in synchronous mode). The FMC_CLK is generated continuously 36*8bab661aSEmmanuel Vadot during asynchronous and synchronous access. By default, the 37*8bab661aSEmmanuel Vadot FMC_CLK is only generated during synchronous access. 38*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 39*8bab661aSEmmanuel Vadot 40*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-mux-enable: 41*8bab661aSEmmanuel Vadot description: Address/Data multiplexed on databus (valid only with 42*8bab661aSEmmanuel Vadot NOR and PSRAM transactions type). By default, Address/Data 43*8bab661aSEmmanuel Vadot are not multiplexed. 44*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 45*8bab661aSEmmanuel Vadot 46*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-buswidth: 47*8bab661aSEmmanuel Vadot description: Data bus width 48*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 49*8bab661aSEmmanuel Vadot enum: [ 8, 16 ] 50*8bab661aSEmmanuel Vadot default: 16 51*8bab661aSEmmanuel Vadot 52*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-waitpol-high: 53*8bab661aSEmmanuel Vadot description: Wait signal polarity (NWAIT signal active high). 54*8bab661aSEmmanuel Vadot By default, NWAIT is active low. 55*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 56*8bab661aSEmmanuel Vadot 57*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-waitcfg-enable: 58*8bab661aSEmmanuel Vadot description: The NWAIT signal indicates wheither the data from the 59*8bab661aSEmmanuel Vadot device are valid or if a wait state must be inserted when accessing 60*8bab661aSEmmanuel Vadot the device in synchronous mode. By default, the NWAIT signal is 61*8bab661aSEmmanuel Vadot active one data cycle before wait state. 62*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 63*8bab661aSEmmanuel Vadot 64*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-wait-enable: 65*8bab661aSEmmanuel Vadot description: The NWAIT signal is enabled (its level is taken into 66*8bab661aSEmmanuel Vadot account after the programmed latency period to insert wait states 67*8bab661aSEmmanuel Vadot if asserted). By default, the NWAIT signal is disabled. 68*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 69*8bab661aSEmmanuel Vadot 70*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-asyncwait-enable: 71*8bab661aSEmmanuel Vadot description: The NWAIT signal is taken into account during asynchronous 72*8bab661aSEmmanuel Vadot transactions. By default, the NWAIT signal is not taken into account 73*8bab661aSEmmanuel Vadot during asynchronous transactions. 74*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 75*8bab661aSEmmanuel Vadot 76*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-cpsize: 77*8bab661aSEmmanuel Vadot description: CRAM page size. The controller splits the burst access 78*8bab661aSEmmanuel Vadot when the memory page is reached. By default, no burst split when 79*8bab661aSEmmanuel Vadot crossing page boundary. 80*8bab661aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 81*8bab661aSEmmanuel Vadot enum: [ 0, 128, 256, 512, 1024 ] 82*8bab661aSEmmanuel Vadot default: 0 83*8bab661aSEmmanuel Vadot 84*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-byte-lane-setup-ns: 85*8bab661aSEmmanuel Vadot description: This property configures the byte lane setup timing 86*8bab661aSEmmanuel Vadot defined in nanoseconds from NBLx low to Chip Select NEx low. 87*8bab661aSEmmanuel Vadot 88*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-address-setup-ns: 89*8bab661aSEmmanuel Vadot description: This property defines the duration of the address setup 90*8bab661aSEmmanuel Vadot phase in nanoseconds used for asynchronous read/write transactions. 91*8bab661aSEmmanuel Vadot 92*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-address-hold-ns: 93*8bab661aSEmmanuel Vadot description: This property defines the duration of the address hold 94*8bab661aSEmmanuel Vadot phase in nanoseconds used for asynchronous multiplexed read/write 95*8bab661aSEmmanuel Vadot transactions. 96*8bab661aSEmmanuel Vadot 97*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-data-setup-ns: 98*8bab661aSEmmanuel Vadot description: This property defines the duration of the data setup phase 99*8bab661aSEmmanuel Vadot in nanoseconds used for asynchronous read/write transactions. 100*8bab661aSEmmanuel Vadot 101*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-bus-turnaround-ns: 102*8bab661aSEmmanuel Vadot description: This property defines the delay in nanoseconds between the 103*8bab661aSEmmanuel Vadot end of current read/write transaction and the next transaction. 104*8bab661aSEmmanuel Vadot 105*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-data-hold-ns: 106*8bab661aSEmmanuel Vadot description: This property defines the duration of the data hold phase 107*8bab661aSEmmanuel Vadot in nanoseconds used for asynchronous read/write transactions. 108*8bab661aSEmmanuel Vadot 109*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-clk-period-ns: 110*8bab661aSEmmanuel Vadot description: This property defines the FMC_CLK output signal period in 111*8bab661aSEmmanuel Vadot nanoseconds. 112*8bab661aSEmmanuel Vadot 113*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-data-latency-ns: 114*8bab661aSEmmanuel Vadot description: This property defines the data latency before reading or 115*8bab661aSEmmanuel Vadot writing the first data in nanoseconds. 116*8bab661aSEmmanuel Vadot 117*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-write-address-setup-ns: 118*8bab661aSEmmanuel Vadot description: This property defines the duration of the address setup 119*8bab661aSEmmanuel Vadot phase in nanoseconds used for asynchronous write transactions. 120*8bab661aSEmmanuel Vadot 121*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-write-address-hold-ns: 122*8bab661aSEmmanuel Vadot description: This property defines the duration of the address hold 123*8bab661aSEmmanuel Vadot phase in nanoseconds used for asynchronous multiplexed write 124*8bab661aSEmmanuel Vadot transactions. 125*8bab661aSEmmanuel Vadot 126*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-write-data-setup-ns: 127*8bab661aSEmmanuel Vadot description: This property defines the duration of the data setup 128*8bab661aSEmmanuel Vadot phase in nanoseconds used for asynchronous write transactions. 129*8bab661aSEmmanuel Vadot 130*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-write-bus-turnaround-ns: 131*8bab661aSEmmanuel Vadot description: This property defines the delay between the end of current 132*8bab661aSEmmanuel Vadot write transaction and the next transaction in nanoseconds. 133*8bab661aSEmmanuel Vadot 134*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-write-data-hold-ns: 135*8bab661aSEmmanuel Vadot description: This property defines the duration of the data hold phase 136*8bab661aSEmmanuel Vadot in nanoseconds used for asynchronous write transactions. 137*8bab661aSEmmanuel Vadot 138*8bab661aSEmmanuel Vadot st,fmc2-ebi-cs-max-low-pulse-ns: 139*8bab661aSEmmanuel Vadot description: This property defines the maximum chip select low pulse 140*8bab661aSEmmanuel Vadot duration in nanoseconds for synchronous transactions. When this timing 141*8bab661aSEmmanuel Vadot reaches 0, the controller splits the current access, toggles NE to 142*8bab661aSEmmanuel Vadot allow device refresh and restarts a new access. 143*8bab661aSEmmanuel Vadot 144*8bab661aSEmmanuel VadotadditionalProperties: true 145