1*c66ec88fSEmmanuel VadotBinding for Synopsys IntelliDDR Multi Protocol Memory Controller 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotThe ZynqMP DDR ECC controller has an optional ECC support in 64-bit and 32-bit 4*c66ec88fSEmmanuel Vadotbus width configurations. 5*c66ec88fSEmmanuel Vadot 6*c66ec88fSEmmanuel VadotThe Zynq DDR ECC controller has an optional ECC support in half-bus width 7*c66ec88fSEmmanuel Vadot(16-bit) configuration. 8*c66ec88fSEmmanuel Vadot 9*c66ec88fSEmmanuel VadotThese both ECC controllers correct single bit ECC errors and detect double bit 10*c66ec88fSEmmanuel VadotECC errors. 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel VadotRequired properties: 13*c66ec88fSEmmanuel Vadot - compatible: One of: 14*c66ec88fSEmmanuel Vadot - 'xlnx,zynq-ddrc-a05' : Zynq DDR ECC controller 15*c66ec88fSEmmanuel Vadot - 'xlnx,zynqmp-ddrc-2.40a' : ZynqMP DDR ECC controller 16*c66ec88fSEmmanuel Vadot - reg: Should contain DDR controller registers location and length. 17*c66ec88fSEmmanuel Vadot 18*c66ec88fSEmmanuel VadotRequired properties for "xlnx,zynqmp-ddrc-2.40a": 19*c66ec88fSEmmanuel Vadot - interrupts: Property with a value describing the interrupt number. 20*c66ec88fSEmmanuel Vadot 21*c66ec88fSEmmanuel VadotExample: 22*c66ec88fSEmmanuel Vadot memory-controller@f8006000 { 23*c66ec88fSEmmanuel Vadot compatible = "xlnx,zynq-ddrc-a05"; 24*c66ec88fSEmmanuel Vadot reg = <0xf8006000 0x1000>; 25*c66ec88fSEmmanuel Vadot }; 26*c66ec88fSEmmanuel Vadot 27*c66ec88fSEmmanuel Vadot mc: memory-controller@fd070000 { 28*c66ec88fSEmmanuel Vadot compatible = "xlnx,zynqmp-ddrc-2.40a"; 29*c66ec88fSEmmanuel Vadot reg = <0x0 0xfd070000 0x0 0x30000>; 30*c66ec88fSEmmanuel Vadot interrupt-parent = <&gic>; 31*c66ec88fSEmmanuel Vadot interrupts = <0 112 4>; 32*c66ec88fSEmmanuel Vadot }; 33