1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx Zynqmp OCM(On-Chip Memory) Controller
8
9maintainers:
10  - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com>
11  - Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
12
13description: |
14  The OCM supports 64-bit wide ECC functionality to detect multi-bit errors
15  and recover from a single-bit memory fault.On a write, if all bytes are
16  being written, the ECC is generated and written into the ECC RAM along with
17  the write-data that is written into the data RAM. If one or more bytes are
18  not written, then the read operation results in an correctable error or
19  uncorrectable error.
20
21properties:
22  compatible:
23    const: xlnx,zynqmp-ocmc-1.0
24
25  reg:
26    maxItems: 1
27
28  interrupts:
29    maxItems: 1
30
31required:
32  - compatible
33  - reg
34  - interrupts
35
36additionalProperties: false
37
38examples:
39  - |
40    #include <dt-bindings/interrupt-controller/arm-gic.h>
41    memory-controller@ff960000 {
42      compatible = "xlnx,zynqmp-ocmc-1.0";
43      reg = <0xff960000 0x1000>;
44      interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
45    };
46