1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Arasan SDHCI Controller
8
9maintainers:
10  - Adrian Hunter <adrian.hunter@intel.com>
11
12allOf:
13  - $ref: mmc-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          contains:
18            const: arasan,sdhci-5.1
19    then:
20      required:
21        - phys
22        - phy-names
23  - if:
24      properties:
25        compatible:
26          contains:
27            enum:
28              - xlnx,zynqmp-8.9a
29              - xlnx,versal-8.9a
30              - xlnx,versal-net-emmc
31    then:
32      properties:
33        clock-output-names:
34          oneOf:
35            - items:
36                - const: clk_out_sd0
37                - const: clk_in_sd0
38            - items:
39                - const: clk_out_sd1
40                - const: clk_in_sd1
41
42properties:
43  compatible:
44    oneOf:
45      - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
46      - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
47      - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
48      - items:
49          - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
50          - const: arasan,sdhci-5.1
51        description:
52          For this device it is strongly suggested to include
53          arasan,soc-ctl-syscon.
54      - items:
55          - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
56          - const: arasan,sdhci-8.9a
57        description:
58          For this device it is strongly suggested to include
59          clock-output-names and '#clock-cells'.
60      - items:
61          - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
62          - const: arasan,sdhci-8.9a
63        description:
64          For this device it is strongly suggested to include
65          clock-output-names and '#clock-cells'.
66      - const: xlnx,versal-net-emmc     # Versal Net eMMC PHY
67        description:
68          For this device it is strongly suggested to include
69          clock-output-names and '#clock-cells'.
70      - items:
71          - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
72          - const: arasan,sdhci-5.1
73        description:
74          For this device it is strongly suggested to include
75          arasan,soc-ctl-syscon.
76      - items:
77          - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
78          - const: arasan,sdhci-5.1
79        description:
80          For this device it is strongly suggested to include
81          arasan,soc-ctl-syscon.
82      - items:
83          - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
84          - const: arasan,sdhci-5.1
85        description:
86          For this device it is strongly suggested to include
87          arasan,soc-ctl-syscon.
88      - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
89        description:
90          For this device it is strongly suggested to include
91          arasan,soc-ctl-syscon.
92      - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
93        description:
94          For this device it is strongly suggested to include
95          arasan,soc-ctl-syscon.
96
97  reg:
98    maxItems: 1
99
100  clocks:
101    minItems: 2
102    maxItems: 3
103
104  clock-names:
105    minItems: 2
106    items:
107      - const: clk_xin
108      - const: clk_ahb
109      - const: gate
110
111  interrupts:
112    maxItems: 1
113
114  phys:
115    maxItems: 1
116
117  phy-names:
118    const: phy_arasan
119
120  resets:
121    maxItems: 1
122
123  arasan,soc-ctl-syscon:
124    $ref: /schemas/types.yaml#/definitions/phandle
125    description:
126      A phandle to a syscon device (see ../mfd/syscon.txt) used to access
127      core corecfg registers. Offsets of registers in this syscon are
128      determined based on the main compatible string for the device.
129
130  clock-output-names:
131    minItems: 1
132    maxItems: 2
133    description:
134      Name of the card clock which will be exposed by this device.
135
136  '#clock-cells':
137    enum: [0, 1]
138    description:
139      With this property in place we will export one or two clocks
140      representing the Card Clock. These clocks are expected to be
141      consumed by our PHY.
142
143  xlnx,fails-without-test-cd:
144    $ref: /schemas/types.yaml#/definitions/flag
145    description:
146      When present, the controller doesn't work when the CD line is not
147      connected properly, and the line is not connected properly.
148      Test mode can be used to force the controller to function.
149
150  xlnx,int-clock-stable-broken:
151    $ref: /schemas/types.yaml#/definitions/flag
152    description:
153      When present, the controller always reports that the internal clock
154      is stable even when it is not.
155
156  xlnx,mio-bank:
157    $ref: /schemas/types.yaml#/definitions/uint32
158    enum: [0, 1, 2]
159    default: 0
160    description:
161      The MIO bank number in which the command and data lines are configured.
162
163dependencies:
164  '#clock-cells': [ clock-output-names ]
165
166required:
167  - compatible
168  - reg
169  - interrupts
170  - clocks
171  - clock-names
172
173unevaluatedProperties: false
174
175examples:
176  - |
177    mmc@e0100000 {
178          compatible = "arasan,sdhci-8.9a";
179          reg = <0xe0100000 0x1000>;
180          clock-names = "clk_xin", "clk_ahb";
181          clocks = <&clkc 21>, <&clkc 32>;
182          interrupt-parent = <&gic>;
183          interrupts = <0 24 4>;
184    };
185
186  - |
187    mmc@e2800000 {
188          compatible = "arasan,sdhci-5.1";
189          reg = <0xe2800000 0x1000>;
190          clock-names = "clk_xin", "clk_ahb";
191          clocks = <&cru 8>, <&cru 18>;
192          interrupt-parent = <&gic>;
193          interrupts = <0 24 4>;
194          phys = <&emmc_phy>;
195          phy-names = "phy_arasan";
196    };
197
198  - |
199    #include <dt-bindings/clock/rk3399-cru.h>
200    #include <dt-bindings/interrupt-controller/arm-gic.h>
201    #include <dt-bindings/interrupt-controller/irq.h>
202    mmc@fe330000 {
203          compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
204          reg = <0xfe330000 0x10000>;
205          interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
206          clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
207          clock-names = "clk_xin", "clk_ahb";
208          arasan,soc-ctl-syscon = <&grf>;
209          assigned-clocks = <&cru SCLK_EMMC>;
210          assigned-clock-rates = <200000000>;
211          clock-output-names = "emmc_cardclock";
212          phys = <&emmc_phy>;
213          phy-names = "phy_arasan";
214          #clock-cells = <0>;
215    };
216
217  - |
218    mmc@ff160000 {
219          compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
220          interrupt-parent = <&gic>;
221          interrupts = <0 48 4>;
222          reg = <0xff160000 0x1000>;
223          clocks = <&clk200>, <&clk200>;
224          clock-names = "clk_xin", "clk_ahb";
225          clock-output-names = "clk_out_sd0", "clk_in_sd0";
226          #clock-cells = <1>;
227          clk-phase-sd-hs = <63>, <72>;
228    };
229
230  - |
231    mmc@f1040000 {
232          compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
233          interrupt-parent = <&gic>;
234          interrupts = <0 126 4>;
235          reg = <0xf1040000 0x10000>;
236          clocks = <&clk200>, <&clk200>;
237          clock-names = "clk_xin", "clk_ahb";
238          clock-output-names = "clk_out_sd0", "clk_in_sd0";
239          #clock-cells = <1>;
240          clk-phase-sd-hs = <132>, <60>;
241    };
242
243  - |
244    #define LGM_CLK_EMMC5
245    #define LGM_CLK_NGI
246    #define LGM_GCLK_EMMC
247    mmc@ec700000 {
248          compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
249          reg = <0xec700000 0x300>;
250          interrupt-parent = <&ioapic1>;
251          interrupts = <44 1>;
252          clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
253                   <&cgu0 LGM_GCLK_EMMC>;
254          clock-names = "clk_xin", "clk_ahb", "gate";
255          clock-output-names = "emmc_cardclock";
256          #clock-cells = <0>;
257          phys = <&emmc_phy>;
258          phy-names = "phy_arasan";
259          arasan,soc-ctl-syscon = <&sysconf>;
260    };
261
262  - |
263    #define LGM_CLK_SDIO
264    #define LGM_GCLK_SDXC
265    mmc@ec600000 {
266          compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
267          reg = <0xec600000 0x300>;
268          interrupt-parent = <&ioapic1>;
269          interrupts = <43 1>;
270          clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
271                   <&cgu0 LGM_GCLK_SDXC>;
272          clock-names = "clk_xin", "clk_ahb", "gate";
273          clock-output-names = "sdxc_cardclock";
274          #clock-cells = <0>;
275          phys = <&sdxc_phy>;
276          phy-names = "phy_arasan";
277          arasan,soc-ctl-syscon = <&sysconf>;
278    };
279
280  - |
281    #define KEEM_BAY_PSS_AUX_EMMC
282    #define KEEM_BAY_PSS_EMMC
283    mmc@33000000 {
284          compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
285          interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
286          reg = <0x33000000 0x300>;
287          clock-names = "clk_xin", "clk_ahb";
288          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
289                   <&scmi_clk KEEM_BAY_PSS_EMMC>;
290          phys = <&emmc_phy>;
291          phy-names = "phy_arasan";
292          assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
293          assigned-clock-rates = <200000000>;
294          clock-output-names = "emmc_cardclock";
295          #clock-cells = <0>;
296          arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
297    };
298
299  - |
300    #define KEEM_BAY_PSS_AUX_SD0
301    #define KEEM_BAY_PSS_SD0
302    mmc@31000000 {
303          compatible = "intel,keembay-sdhci-5.1-sd";
304          interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
305          reg = <0x31000000 0x300>;
306          clock-names = "clk_xin", "clk_ahb";
307          clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
308                   <&scmi_clk KEEM_BAY_PSS_SD0>;
309          arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
310    };
311