1Marvell Xenon SDHCI Controller device tree bindings
2This file documents differences between the core mmc properties
3described by mmc.txt and the properties used by the Xenon implementation.
4
5Multiple SDHCs might be put into a single Xenon IP, to save size and cost.
6Each SDHC is independent and owns independent resources, such as register sets,
7clock and PHY.
8Each SDHC should have an independent device tree node.
9
10Required Properties:
11- compatible: should be one of the following
12  - "marvell,armada-3700-sdhci": For controllers on Armada-3700 SoC.
13  Must provide a second register area and marvell,pad-type.
14  - "marvell,armada-ap806-sdhci": For controllers on Armada AP806.
15  - "marvell,armada-ap807-sdhci": For controllers on Armada AP807.
16  - "marvell,armada-cp110-sdhci": For controllers on Armada CP110.
17
18- clocks:
19  Array of clocks required for SDHC.
20  Require at least input clock for Xenon IP core. For Armada AP806 and
21  CP110, the AXI clock is also mandatory.
22
23- clock-names:
24  Array of names corresponding to clocks property.
25  The input clock for Xenon IP core should be named as "core".
26  The input clock for the AXI bus must be named as "axi".
27
28- reg:
29  * For "marvell,armada-3700-sdhci", two register areas.
30    The first one for Xenon IP register. The second one for the Armada 3700 SoC
31    PHY PAD Voltage Control register.
32    Please follow the examples with compatible "marvell,armada-3700-sdhci"
33    in below.
34    Please also check property marvell,pad-type in below.
35
36  * For other compatible strings, one register area for Xenon IP.
37
38Optional Properties:
39- marvell,xenon-sdhc-id:
40  Indicate the corresponding bit index of current SDHC in
41  SDHC System Operation Control Register Bit[7:0].
42  Set/clear the corresponding bit to enable/disable current SDHC.
43  If Xenon IP contains only one SDHC, this property is optional.
44
45- marvell,xenon-phy-type:
46  Xenon support multiple types of PHYs.
47  To select eMMC 5.1 PHY, set:
48  marvell,xenon-phy-type = "emmc 5.1 phy"
49  eMMC 5.1 PHY is the default choice if this property is not provided.
50  To select eMMC 5.0 PHY, set:
51  marvell,xenon-phy-type = "emmc 5.0 phy"
52
53  All those types of PHYs can support eMMC, SD and SDIO.
54  Please note that this property only presents the type of PHY.
55  It doesn't stand for the entire SDHC type or property.
56  For example, "emmc 5.1 phy" doesn't mean that this Xenon SDHC only
57  supports eMMC 5.1.
58
59- marvell,xenon-phy-znr:
60  Set PHY ZNR value.
61  Only available for eMMC PHY.
62  Valid range = [0:0x1F].
63  ZNR is set as 0xF by default if this property is not provided.
64
65- marvell,xenon-phy-zpr:
66  Set PHY ZPR value.
67  Only available for eMMC PHY.
68  Valid range = [0:0x1F].
69  ZPR is set as 0xF by default if this property is not provided.
70
71- marvell,xenon-phy-nr-success-tun:
72  Set the number of required consecutive successful sampling points
73  used to identify a valid sampling window, in tuning process.
74  Valid range = [1:7].
75  Set as 0x4 by default if this property is not provided.
76
77- marvell,xenon-phy-tun-step-divider:
78  Set the divider for calculating TUN_STEP.
79  Set as 64 by default if this property is not provided.
80
81- marvell,xenon-phy-slow-mode:
82  If this property is selected, transfers will bypass PHY.
83  Only available when bus frequency lower than 55MHz in SDR mode.
84  Disabled by default. Please only try this property if timing issues
85  always occur with PHY enabled in eMMC HS SDR, SD SDR12, SD SDR25,
86  SD Default Speed and HS mode and eMMC legacy speed mode.
87
88- marvell,xenon-tun-count:
89  Xenon SDHC SoC usually doesn't provide re-tuning counter in
90  Capabilities Register 3 Bit[11:8].
91  This property provides the re-tuning counter.
92  If this property is not set, default re-tuning counter will
93  be set as 0x9 in driver.
94
95- marvell,pad-type:
96  Type of Armada 3700 SoC PHY PAD Voltage Controller register.
97  Only valid when "marvell,armada-3700-sdhci" is selected.
98  Two types: "sd" and "fixed-1-8v".
99  If "sd" is selected, SoC PHY PAD is set as 3.3V at the beginning and is
100  switched to 1.8V when later in higher speed mode.
101  If "fixed-1-8v" is selected, SoC PHY PAD is fixed 1.8V, such as for eMMC.
102  Please follow the examples with compatible "marvell,armada-3700-sdhci"
103  in below.
104
105Example:
106- For eMMC:
107
108	sdhci@aa0000 {
109		compatible = "marvell,armada-ap806-sdhci";
110		reg = <0xaa0000 0x1000>;
111		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
112		clocks = <&emmc_clk>,<&axi_clk>;
113		clock-names = "core", "axi";
114		bus-width = <4>;
115		marvell,xenon-phy-slow-mode;
116		marvell,xenon-tun-count = <11>;
117		non-removable;
118		no-sd;
119		no-sdio;
120
121		/* Vmmc and Vqmmc are both fixed */
122	};
123
124- For SD/SDIO:
125
126	sdhci@ab0000 {
127		compatible = "marvell,armada-cp110-sdhci";
128		reg = <0xab0000 0x1000>;
129		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
130		vqmmc-supply = <&sd_vqmmc_regulator>;
131		vmmc-supply = <&sd_vmmc_regulator>;
132		clocks = <&sdclk>, <&axi_clk>;
133		clock-names = "core", "axi";
134		bus-width = <4>;
135		marvell,xenon-tun-count = <9>;
136	};
137
138- For eMMC with compatible "marvell,armada-3700-sdhci":
139
140	sdhci@aa0000 {
141		compatible = "marvell,armada-3700-sdhci";
142		reg = <0xaa0000 0x1000>,
143		      <phy_addr 0x4>;
144		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>
145		clocks = <&emmcclk>;
146		clock-names = "core";
147		bus-width = <8>;
148		mmc-ddr-1_8v;
149		mmc-hs400-1_8v;
150		non-removable;
151		no-sd;
152		no-sdio;
153
154		/* Vmmc and Vqmmc are both fixed */
155
156		marvell,pad-type = "fixed-1-8v";
157	};
158
159- For SD/SDIO with compatible "marvell,armada-3700-sdhci":
160
161	sdhci@ab0000 {
162		compatible = "marvell,armada-3700-sdhci";
163		reg = <0xab0000 0x1000>,
164		      <phy_addr 0x4>;
165		interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>
166		vqmmc-supply = <&sd_regulator>;
167		/* Vmmc is fixed */
168		clocks = <&sdclk>;
169		clock-names = "core";
170		bus-width = <4>;
171
172		marvell,pad-type = "sd";
173	};
174