1* Andestech L2 cache Controller
2
3The level-2 cache controller plays an important role in reducing memory latency
4for high performance systems, such as thoese designs with AndesCore processors.
5Level-2 cache controller in general enhances overall system performance
6signigicantly and the system power consumption might be reduced as well by
7reducing DRAM accesses.
8
9This binding specifies what properties must be available in the device tree
10representation of an Andestech L2 cache controller.
11
12Required properties:
13	- compatible:
14		Usage: required
15		Value type: <string>
16		Definition: "andestech,atl2c"
17	- reg : Physical base address and size of cache controller's memory mapped
18	- cache-unified : Specifies the cache is a unified cache.
19	- cache-level : Should be set to 2 for a level 2 cache.
20
21* Example
22
23	cache-controller@e0500000 {
24		compatible = "andestech,atl2c";
25		reg = <0xe0500000 0x1000>;
26		cache-unified;
27		cache-level = <2>;
28	};
29