1Mediatek MT7530 Ethernet switch
2================================
3
4Required properties:
5
6- compatible: may be compatible = "mediatek,mt7530"
7	or compatible = "mediatek,mt7621"
8	or compatible = "mediatek,mt7531"
9- #address-cells: Must be 1.
10- #size-cells: Must be 0.
11- mediatek,mcm: Boolean; if defined, indicates that either MT7530 is the part
12	on multi-chip module belong to MT7623A has or the remotely standalone
13	chip as the function MT7623N reference board provided for.
14
15If compatible mediatek,mt7530 is set then the following properties are required
16
17- core-supply: Phandle to the regulator node necessary for the core power.
18- io-supply: Phandle to the regulator node necessary for the I/O power.
19	See Documentation/devicetree/bindings/regulator/mt6323-regulator.txt
20	for details for the regulator setup on these boards.
21
22If the property mediatek,mcm isn't defined, following property is required
23
24- reset-gpios: Should be a gpio specifier for a reset line.
25
26Else, following properties are required
27
28- resets : Phandle pointing to the system reset controller with
29	line index for the ethsys.
30- reset-names : Should be set to "mcm".
31
32Required properties for the child nodes within ports container:
33
34- reg: Port address described must be 6 for CPU port and from 0 to 5 for
35	user ports.
36- phy-mode: String, the following values are acceptable for port labeled
37	"cpu":
38	If compatible mediatek,mt7530 or mediatek,mt7621 is set,
39	must be either "trgmii" or "rgmii"
40	If compatible mediatek,mt7531 is set,
41	must be either "sgmii", "1000base-x" or "2500base-x"
42
43Port 5 of mt7530 and mt7621 switch is muxed between:
441. GMAC5: GMAC5 can interface with another external MAC or PHY.
452. PHY of port 0 or port 4: PHY interfaces with an external MAC like 2nd GMAC
46   of the SOC. Used in many setups where port 0/4 becomes the WAN port.
47   Note: On a MT7621 SOC with integrated switch: 2nd GMAC can only connected to
48	 GMAC5 when the gpios for RGMII2 (GPIO 22-33) are not used and not
49	 connected to external component!
50
51Port 5 modes/configurations:
521. Port 5 is disabled and isolated: An external phy can interface to the 2nd
53   GMAC of the SOC.
54   In the case of a build-in MT7530 switch, port 5 shares the RGMII bus with 2nd
55   GMAC and an optional external phy. Mind the GPIO/pinctl settings of the SOC!
562. Port 5 is muxed to PHY of port 0/4: Port 0/4 interfaces with 2nd GMAC.
57   It is a simple MAC to PHY interface, port 5 needs to be setup for xMII mode
58   and RGMII delay.
593. Port 5 is muxed to GMAC5 and can interface to an external phy.
60   Port 5 becomes an extra switch port.
61   Only works on platform where external phy TX<->RX lines are swapped.
62   Like in the Ubiquiti ER-X-SFP.
634. Port 5 is muxed to GMAC5 and interfaces with the 2nd GAMC as 2nd CPU port.
64   Currently a 2nd CPU port is not supported by DSA code.
65
66Depending on how the external PHY is wired:
671. normal: The PHY can only connect to 2nd GMAC but not to the switch
682. swapped: RGMII TX, RX are swapped; external phy interface with the switch as
69   a ethernet port. But can't interface to the 2nd GMAC.
70
71Based on the DT the port 5 mode is configured.
72
73Driver tries to lookup the phy-handle of the 2nd GMAC of the master device.
74When phy-handle matches PHY of port 0 or 4 then port 5 set-up as mode 2.
75phy-mode must be set, see also example 2 below!
76 * mt7621: phy-mode = "rgmii-txid";
77 * mt7623: phy-mode = "rgmii";
78
79Optional properties:
80
81- gpio-controller: Boolean; if defined, MT7530's LED controller will run on
82	GPIO mode.
83- #gpio-cells: Must be 2 if gpio-controller is defined.
84
85See Documentation/devicetree/bindings/net/dsa/dsa.txt for a list of additional
86required, optional properties and how the integrated switch subnodes must
87be specified.
88
89Example:
90
91	&mdio0 {
92		switch@0 {
93			compatible = "mediatek,mt7530";
94			#address-cells = <1>;
95			#size-cells = <0>;
96			reg = <0>;
97
98			core-supply = <&mt6323_vpa_reg>;
99			io-supply = <&mt6323_vemc3v3_reg>;
100			reset-gpios = <&pio 33 0>;
101
102			ports {
103				#address-cells = <1>;
104				#size-cells = <0>;
105				reg = <0>;
106				port@0 {
107					reg = <0>;
108					label = "lan0";
109				};
110
111				port@1 {
112					reg = <1>;
113					label = "lan1";
114				};
115
116				port@2 {
117					reg = <2>;
118					label = "lan2";
119				};
120
121				port@3 {
122					reg = <3>;
123					label = "lan3";
124				};
125
126				port@4 {
127					reg = <4>;
128					label = "wan";
129				};
130
131				port@6 {
132					reg = <6>;
133					label = "cpu";
134					ethernet = <&gmac0>;
135					phy-mode = "trgmii";
136					fixed-link {
137						speed = <1000>;
138						full-duplex;
139					};
140				};
141			};
142		};
143	};
144
145Example 2: MT7621: Port 4 is WAN port: 2nd GMAC -> Port 5 -> PHY port 4.
146
147&eth {
148	gmac0: mac@0 {
149		compatible = "mediatek,eth-mac";
150		reg = <0>;
151		phy-mode = "rgmii";
152
153		fixed-link {
154			speed = <1000>;
155			full-duplex;
156			pause;
157		};
158	};
159
160	gmac1: mac@1 {
161		compatible = "mediatek,eth-mac";
162		reg = <1>;
163		phy-mode = "rgmii-txid";
164		phy-handle = <&phy4>;
165	};
166
167	mdio: mdio-bus {
168		#address-cells = <1>;
169		#size-cells = <0>;
170
171		/* Internal phy */
172		phy4: ethernet-phy@4 {
173			reg = <4>;
174		};
175
176		mt7530: switch@1f {
177			compatible = "mediatek,mt7621";
178			#address-cells = <1>;
179			#size-cells = <0>;
180			reg = <0x1f>;
181			pinctrl-names = "default";
182			mediatek,mcm;
183
184			resets = <&rstctrl 2>;
185			reset-names = "mcm";
186
187			ports {
188				#address-cells = <1>;
189				#size-cells = <0>;
190
191				port@0 {
192					reg = <0>;
193					label = "lan0";
194				};
195
196				port@1 {
197					reg = <1>;
198					label = "lan1";
199				};
200
201				port@2 {
202					reg = <2>;
203					label = "lan2";
204				};
205
206				port@3 {
207					reg = <3>;
208					label = "lan3";
209				};
210
211/* Commented out. Port 4 is handled by 2nd GMAC.
212				port@4 {
213					reg = <4>;
214					label = "lan4";
215				};
216*/
217
218				cpu_port0: port@6 {
219					reg = <6>;
220					label = "cpu";
221					ethernet = <&gmac0>;
222					phy-mode = "rgmii";
223
224					fixed-link {
225						speed = <1000>;
226						full-duplex;
227						pause;
228					};
229				};
230			};
231		};
232	};
233};
234
235Example 3: MT7621: Port 5 is connected to external PHY: Port 5 -> external PHY.
236
237&eth {
238	gmac0: mac@0 {
239		compatible = "mediatek,eth-mac";
240		reg = <0>;
241		phy-mode = "rgmii";
242
243		fixed-link {
244			speed = <1000>;
245			full-duplex;
246			pause;
247		};
248	};
249
250	mdio: mdio-bus {
251		#address-cells = <1>;
252		#size-cells = <0>;
253
254		/* External phy */
255		ephy5: ethernet-phy@7 {
256			reg = <7>;
257		};
258
259		mt7530: switch@1f {
260			compatible = "mediatek,mt7621";
261			#address-cells = <1>;
262			#size-cells = <0>;
263			reg = <0x1f>;
264			pinctrl-names = "default";
265			mediatek,mcm;
266
267			resets = <&rstctrl 2>;
268			reset-names = "mcm";
269
270			ports {
271				#address-cells = <1>;
272				#size-cells = <0>;
273
274				port@0 {
275					reg = <0>;
276					label = "lan0";
277				};
278
279				port@1 {
280					reg = <1>;
281					label = "lan1";
282				};
283
284				port@2 {
285					reg = <2>;
286					label = "lan2";
287				};
288
289				port@3 {
290					reg = <3>;
291					label = "lan3";
292				};
293
294				port@4 {
295					reg = <4>;
296					label = "lan4";
297				};
298
299				port@5 {
300					reg = <5>;
301					label = "lan5";
302					phy-mode = "rgmii";
303					phy-handle = <&ephy5>;
304				};
305
306				cpu_port0: port@6 {
307					reg = <6>;
308					label = "cpu";
309					ethernet = <&gmac0>;
310					phy-mode = "rgmii";
311
312					fixed-link {
313						speed = <1000>;
314						full-duplex;
315						pause;
316					};
317				};
318			};
319		};
320	};
321};
322