1Microchip Ocelot switch driver family
2=====================================
3
4Felix
5-----
6
7Currently the switches supported by the felix driver are:
8
9- VSC9959 (Felix)
10- VSC9953 (Seville)
11
12The VSC9959 switch is found in the NXP LS1028A. It is a PCI device, part of the
13larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
14of the PCIe root complex node and its "reg" property conforms to the parent
15node bindings:
16
17* reg: Specifies PCIe Device Number and Function Number of the endpoint device,
18  in this case for the Ethernet L2Switch it is PF5 (of device 0, bus 0).
19
20It does not require a "compatible" string.
21
22The interrupt line is used to signal availability of PTP TX timestamps and for
23TSN frame preemption.
24
25For the external switch ports, depending on board configuration, "phy-mode" and
26"phy-handle" are populated by board specific device tree instances. Ports 4 and
275 are fixed as internal ports in the NXP LS1028A instantiation.
28
29The CPU port property ("ethernet") configures the feature called "NPI port" in
30the Ocelot hardware core. The CPU port in Ocelot is a set of queues, which are
31connected, in the Node Processor Interface (NPI) mode, to an Ethernet port.
32By default, in fsl-ls1028a.dtsi, the NPI port is assigned to the internal
332.5Gbps port@4, but can be moved to the 1Gbps port@5, depending on the specific
34use case.  Moving the NPI port to an external switch port is hardware possible,
35but there is no platform support for the Linux system on the LS1028A chip to
36operate as an entire slave DSA chip.  NPI functionality (and therefore DSA
37tagging) is supported on a single port at a time.
38
39Any port can be disabled (and in fsl-ls1028a.dtsi, they are indeed all disabled
40by default, and should be enabled on a per-board basis). But if any external
41switch port is enabled at all, the ENETC PF2 (enetc_port2) should be enabled as
42well, regardless of whether it is configured as the DSA master or not. This is
43because the Felix PHYLINK implementation accesses the MAC PCS registers, which
44in hardware truly belong to the ENETC port #2 and not to Felix.
45
46Supported PHY interface types (appropriate SerDes protocol setting changes are
47needed in the RCW binary):
48
49* phy_mode = "internal": on ports 4 and 5
50* phy_mode = "sgmii": on ports 0, 1, 2, 3
51* phy_mode = "qsgmii": on ports 0, 1, 2, 3
52* phy_mode = "usxgmii": on ports 0, 1, 2, 3
53* phy_mode = "2500base-x": on ports 0, 1, 2, 3
54
55For the rest of the device tree binding definitions, which are standard DSA and
56PCI, refer to the following documents:
57
58Documentation/devicetree/bindings/net/dsa/dsa.txt
59Documentation/devicetree/bindings/pci/pci.txt
60
61Example:
62
63&soc {
64	pcie@1f0000000 { /* Integrated Endpoint Root Complex */
65		ethernet-switch@0,5 {
66			reg = <0x000500 0 0 0 0>;
67			/* IEP INT_B */
68			interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
69
70			ports {
71				#address-cells = <1>;
72				#size-cells = <0>;
73
74				/* External ports */
75				port@0 {
76					reg = <0>;
77					label = "swp0";
78				};
79
80				port@1 {
81					reg = <1>;
82					label = "swp1";
83				};
84
85				port@2 {
86					reg = <2>;
87					label = "swp2";
88				};
89
90				port@3 {
91					reg = <3>;
92					label = "swp3";
93				};
94
95				/* Tagging CPU port */
96				port@4 {
97					reg = <4>;
98					ethernet = <&enetc_port2>;
99					phy-mode = "internal";
100
101					fixed-link {
102						speed = <2500>;
103						full-duplex;
104					};
105				};
106
107				/* Non-tagging CPU port */
108				port@5 {
109					reg = <5>;
110					phy-mode = "internal";
111					status = "disabled";
112
113					fixed-link {
114						speed = <1000>;
115						full-duplex;
116					};
117				};
118			};
119		};
120	};
121};
122
123The VSC9953 switch is found inside NXP T1040. It is a platform device with the
124following required properties:
125
126- compatible:
127	Must be "mscc,vsc9953-switch".
128
129Supported PHY interface types (appropriate SerDes protocol setting changes are
130needed in the RCW binary):
131
132* phy_mode = "internal": on ports 8 and 9
133* phy_mode = "sgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
134* phy_mode = "qsgmii": on ports 0, 1, 2, 3, 4, 5, 6, 7
135
136Example:
137
138&soc {
139	ethernet-switch@800000 {
140		#address-cells = <0x1>;
141		#size-cells = <0x0>;
142		compatible = "mscc,vsc9953-switch";
143		little-endian;
144		reg = <0x800000 0x290000>;
145
146		ports {
147			#address-cells = <0x1>;
148			#size-cells = <0x0>;
149
150			port@0 {
151				reg = <0x0>;
152				label = "swp0";
153			};
154
155			port@1 {
156				reg = <0x1>;
157				label = "swp1";
158			};
159
160			port@2 {
161				reg = <0x2>;
162				label = "swp2";
163			};
164
165			port@3 {
166				reg = <0x3>;
167				label = "swp3";
168			};
169
170			port@4 {
171				reg = <0x4>;
172				label = "swp4";
173			};
174
175			port@5 {
176				reg = <0x5>;
177				label = "swp5";
178			};
179
180			port@6 {
181				reg = <0x6>;
182				label = "swp6";
183			};
184
185			port@7 {
186				reg = <0x7>;
187				label = "swp7";
188			};
189
190			port@8 {
191				reg = <0x8>;
192				phy-mode = "internal";
193				ethernet = <&enet0>;
194
195				fixed-link {
196					speed = <2500>;
197					full-duplex;
198				};
199			};
200
201			port@9 {
202				reg = <0x9>;
203				phy-mode = "internal";
204				status = "disabled";
205
206				fixed-link {
207					speed = <2500>;
208					full-duplex;
209				};
210			};
211		};
212	};
213};
214