1* Qualcomm Atheros QCA8xxx switch family
2
3Required properties:
4
5- compatible: should be one of:
6    "qca,qca8327"
7    "qca,qca8334"
8    "qca,qca8337"
9
10- #size-cells: must be 0
11- #address-cells: must be 1
12
13Optional properties:
14
15- reset-gpios: GPIO to be used to reset the whole device
16
17Subnodes:
18
19The integrated switch subnode should be specified according to the binding
20described in dsa/dsa.txt. If the QCA8K switch is connect to a SoC's external
21mdio-bus each subnode describing a port needs to have a valid phandle
22referencing the internal PHY it is connected to. This is because there's no
23N:N mapping of port and PHY id.
24To declare the internal mdio-bus configuration, declare a mdio node in the
25switch node and declare the phandle for the port referencing the internal
26PHY is connected to. In this config a internal mdio-bus is registered and
27the mdio MASTER is used as communication.
28
29Don't use mixed external and internal mdio-bus configurations, as this is
30not supported by the hardware.
31
32The CPU port of this switch is always port 0.
33
34A CPU port node has the following optional node:
35
36- fixed-link            : Fixed-link subnode describing a link to a non-MDIO
37                          managed entity. See
38                          Documentation/devicetree/bindings/net/fixed-link.txt
39                          for details.
40
41For QCA8K the 'fixed-link' sub-node supports only the following properties:
42
43- 'speed' (integer, mandatory), to indicate the link speed. Accepted
44  values are 10, 100 and 1000
45- 'full-duplex' (boolean, optional), to indicate that full duplex is
46  used. When absent, half duplex is assumed.
47
48Examples:
49
50for the external mdio-bus configuration:
51
52	&mdio0 {
53		phy_port1: phy@0 {
54			reg = <0>;
55		};
56
57		phy_port2: phy@1 {
58			reg = <1>;
59		};
60
61		phy_port3: phy@2 {
62			reg = <2>;
63		};
64
65		phy_port4: phy@3 {
66			reg = <3>;
67		};
68
69		phy_port5: phy@4 {
70			reg = <4>;
71		};
72
73		switch@10 {
74			compatible = "qca,qca8337";
75			#address-cells = <1>;
76			#size-cells = <0>;
77
78			reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
79			reg = <0x10>;
80
81			ports {
82				#address-cells = <1>;
83				#size-cells = <0>;
84				port@0 {
85					reg = <0>;
86					label = "cpu";
87					ethernet = <&gmac1>;
88					phy-mode = "rgmii";
89					fixed-link {
90						speed = 1000;
91						full-duplex;
92					};
93				};
94
95				port@1 {
96					reg = <1>;
97					label = "lan1";
98					phy-handle = <&phy_port1>;
99				};
100
101				port@2 {
102					reg = <2>;
103					label = "lan2";
104					phy-handle = <&phy_port2>;
105				};
106
107				port@3 {
108					reg = <3>;
109					label = "lan3";
110					phy-handle = <&phy_port3>;
111				};
112
113				port@4 {
114					reg = <4>;
115					label = "lan4";
116					phy-handle = <&phy_port4>;
117				};
118
119				port@5 {
120					reg = <5>;
121					label = "wan";
122					phy-handle = <&phy_port5>;
123				};
124			};
125		};
126	};
127
128for the internal master mdio-bus configuration:
129
130	&mdio0 {
131		switch@10 {
132			compatible = "qca,qca8337";
133			#address-cells = <1>;
134			#size-cells = <0>;
135
136			reset-gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
137			reg = <0x10>;
138
139			ports {
140				#address-cells = <1>;
141				#size-cells = <0>;
142
143				port@0 {
144					reg = <0>;
145					label = "cpu";
146					ethernet = <&gmac1>;
147					phy-mode = "rgmii";
148					fixed-link {
149						speed = 1000;
150						full-duplex;
151					};
152				};
153
154				port@1 {
155					reg = <1>;
156					label = "lan1";
157					phy-mode = "internal";
158					phy-handle = <&phy_port1>;
159				};
160
161				port@2 {
162					reg = <2>;
163					label = "lan2";
164					phy-mode = "internal";
165					phy-handle = <&phy_port2>;
166				};
167
168				port@3 {
169					reg = <3>;
170					label = "lan3";
171					phy-mode = "internal";
172					phy-handle = <&phy_port3>;
173				};
174
175				port@4 {
176					reg = <4>;
177					label = "lan4";
178					phy-mode = "internal";
179					phy-handle = <&phy_port4>;
180				};
181
182				port@5 {
183					reg = <5>;
184					label = "wan";
185					phy-mode = "internal";
186					phy-handle = <&phy_port5>;
187				};
188			};
189
190			mdio {
191				#address-cells = <1>;
192				#size-cells = <0>;
193
194				phy_port1: phy@0 {
195					reg = <0>;
196				};
197
198				phy_port2: phy@1 {
199					reg = <1>;
200				};
201
202				phy_port3: phy@2 {
203					reg = <2>;
204				};
205
206				phy_port4: phy@3 {
207					reg = <3>;
208				};
209
210				phy_port5: phy@4 {
211					reg = <4>;
212				};
213			};
214		};
215	};
216