1MediaTek DWMAC glue layer controller
2
3This file documents platform glue layer for stmmac.
4Please see stmmac.txt for the other unchanged properties.
5
6The device node has following properties.
7
8Required properties:
9- compatible:  Should be "mediatek,mt2712-gmac" for MT2712 SoC
10- reg:  Address and length of the register set for the device
11- interrupts:  Should contain the MAC interrupts
12- interrupt-names: Should contain a list of interrupt names corresponding to
13	the interrupts in the interrupts property, if available.
14	Should be "macirq" for the main MAC IRQ
15- clocks: Must contain a phandle for each entry in clock-names.
16- clock-names: The name of the clock listed in the clocks property. These are
17	"axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
18- mac-address: See ethernet.txt in the same directory
19- phy-mode: See ethernet.txt in the same directory
20- mediatek,pericfg: A phandle to the syscon node that control ethernet
21	interface and timing delay.
22
23Optional properties:
24- mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
25	It should be defined for RGMII/MII interface.
26	It should be defined for RMII interface when the reference clock is from MT2712 SoC.
27- mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
28	It should be defined for RGMII/MII interface.
29	It should be defined for RMII interface.
30Both delay properties need to be a multiple of 170 for RGMII interface,
31or will round down. Range 0~31*170.
32Both delay properties need to be a multiple of 550 for MII/RMII interface,
33or will round down. Range 0~31*550.
34
35- mediatek,rmii-rxc: boolean property, if present indicates that the RMII
36	reference clock, which is from external PHYs, is connected to RXC pin
37	on MT2712 SoC.
38	Otherwise, is connected to TXC pin.
39- mediatek,rmii-clk-from-mac: boolean property, if present indicates that
40	MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
41- mediatek,txc-inverse: boolean property, if present indicates that
42	1. tx clock will be inversed in MII/RGMII case,
43	2. tx clock inside MAC will be inversed relative to reference clock
44	   which is from external PHYs in RMII case, and it rarely happen.
45	3. the reference clock, which outputs to TXC pin will be inversed in RMII case
46	   when the reference clock is from MT2712 SoC.
47- mediatek,rxc-inverse: boolean property, if present indicates that
48	1. rx clock will be inversed in MII/RGMII case.
49	2. reference clock will be inversed when arrived at MAC in RMII case, when
50	   the reference clock is from external PHYs.
51	3. the inside clock, which be sent to MAC, will be inversed in RMII case when
52	   the reference clock is from MT2712 SoC.
53- assigned-clocks: mac_main and ptp_ref clocks
54- assigned-clock-parents: parent clocks of the assigned clocks
55
56Example:
57	eth: ethernet@1101c000 {
58		compatible = "mediatek,mt2712-gmac";
59		reg = <0 0x1101c000 0 0x1300>;
60		interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
61		interrupt-names = "macirq";
62		phy-mode ="rgmii-rxid";
63		mac-address = [00 55 7b b5 7d f7];
64		clock-names = "axi",
65			      "apb",
66			      "mac_main",
67			      "ptp_ref",
68			      "rmii_internal";
69		clocks = <&pericfg CLK_PERI_GMAC>,
70			 <&pericfg CLK_PERI_GMAC_PCLK>,
71			 <&topckgen CLK_TOP_ETHER_125M_SEL>,
72			 <&topckgen CLK_TOP_ETHER_50M_SEL>,
73			 <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
74		assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
75				  <&topckgen CLK_TOP_ETHER_50M_SEL>,
76				  <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
77		assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
78					 <&topckgen CLK_TOP_APLL1_D3>,
79					 <&topckgen CLK_TOP_ETHERPLL_50M>;
80		power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
81		mediatek,pericfg = <&pericfg>;
82		mediatek,tx-delay-ps = <1530>;
83		mediatek,rx-delay-ps = <1530>;
84		mediatek,rmii-rxc;
85		mediatek,txc-inverse;
86		mediatek,rxc-inverse;
87		snps,txpbl = <1>;
88		snps,rxpbl = <1>;
89		snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
90		snps,reset-active-low;
91	};
92