1Microsemi MII Management Controller (MIIM) / MDIO
2=================================================
3
4Properties:
5- compatible: must be "mscc,ocelot-miim"
6- reg: The base address of the MDIO bus controller register bank. Optionally, a
7  second register bank can be defined if there is an associated reset register
8  for internal PHYs
9- #address-cells: Must be <1>.
10- #size-cells: Must be <0>.  MDIO addresses have no size component.
11- interrupts: interrupt specifier (refer to the interrupt binding)
12
13Typically an MDIO bus might have several children.
14
15Example:
16	mdio@107009c {
17		#address-cells = <1>;
18		#size-cells = <0>;
19		compatible = "mscc,ocelot-miim";
20		reg = <0x107009c 0x36>, <0x10700f0 0x8>;
21		interrupts = <14>;
22
23		phy0: ethernet-phy@0 {
24			reg = <0>;
25		};
26	};
27