1Rockchip SoC RK3288 10/100/1000 Ethernet driver(GMAC)
2
3The device node has following properties.
4
5Required properties:
6 - compatible: should be "rockchip,<name>-gamc"
7   "rockchip,px30-gmac":   found on PX30 SoCs
8   "rockchip,rk3128-gmac": found on RK312x SoCs
9   "rockchip,rk3228-gmac": found on RK322x SoCs
10   "rockchip,rk3288-gmac": found on RK3288 SoCs
11   "rockchip,rk3328-gmac": found on RK3328 SoCs
12   "rockchip,rk3366-gmac": found on RK3366 SoCs
13   "rockchip,rk3368-gmac": found on RK3368 SoCs
14   "rockchip,rk3399-gmac": found on RK3399 SoCs
15   "rockchip,rv1108-gmac": found on RV1108 SoCs
16 - reg: addresses and length of the register sets for the device.
17 - interrupts: Should contain the GMAC interrupts.
18 - interrupt-names: Should contain the interrupt names "macirq".
19 - rockchip,grf: phandle to the syscon grf used to control speed and mode.
20 - clocks: <&cru SCLK_MAC>: clock selector for main clock, from PLL or PHY.
21	   <&cru SCLK_MAC_PLL>: PLL clock for SCLK_MAC
22	   <&cru SCLK_MAC_RX>: clock gate for RX
23	   <&cru SCLK_MAC_TX>: clock gate for TX
24	   <&cru SCLK_MACREF>: clock gate for RMII referce clock
25	   <&cru SCLK_MACREF_OUT> clock gate for RMII reference clock output
26	   <&cru ACLK_GMAC>: AXI clock gate for GMAC
27	   <&cru PCLK_GMAC>: APB clock gate for GMAC
28 - clock-names: One name for each entry in the clocks property.
29 - phy-mode: See ethernet.txt file in the same directory.
30 - pinctrl-names: Names corresponding to the numbered pinctrl states.
31 - pinctrl-0: pin-control mode. can be <&rgmii_pins> or <&rmii_pins>.
32 - clock_in_out: For RGMII, it must be "input", means main clock(125MHz)
33   is not sourced from SoC's PLL, but input from PHY; For RMII, "input" means
34   PHY provides the reference clock(50MHz), "output" means GMAC provides the
35   reference clock.
36 - snps,reset-gpio       gpio number for phy reset.
37 - snps,reset-active-low boolean flag to indicate if phy reset is active low.
38 - assigned-clocks: main clock, should be <&cru SCLK_MAC>;
39 - assigned-clock-parents = parent of main clock.
40   can be <&ext_gmac> or <&cru SCLK_MAC_PLL>.
41
42Optional properties:
43 - tx_delay: Delay value for TXD timing. Range value is 0~0x7F, 0x30 as default.
44 - rx_delay: Delay value for RXD timing. Range value is 0~0x7F, 0x10 as default.
45 - phy-supply: phandle to a regulator if the PHY needs one
46
47Example:
48
49gmac: ethernet@ff290000 {
50	compatible = "rockchip,rk3288-gmac";
51	reg = <0xff290000 0x10000>;
52	interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
53	interrupt-names = "macirq";
54	rockchip,grf = <&grf>;
55	clocks = <&cru SCLK_MAC>,
56		<&cru SCLK_MAC_RX>, <&cru SCLK_MAC_TX>,
57		<&cru SCLK_MACREF>, <&cru SCLK_MACREF_OUT>,
58		<&cru ACLK_GMAC>, <&cru PCLK_GMAC>;
59	clock-names = "stmmaceth",
60		"mac_clk_rx", "mac_clk_tx",
61		"clk_mac_ref", "clk_mac_refout",
62		"aclk_mac", "pclk_mac";
63	phy-mode = "rgmii";
64	pinctrl-names = "default";
65	pinctrl-0 = <&rgmii_pins /*&rmii_pins*/>;
66
67	clock_in_out = "input";
68	snps,reset-gpio = <&gpio4 7 0>;
69	snps,reset-active-low;
70
71	assigned-clocks = <&cru SCLK_MAC>;
72	assigned-clock-parents = <&ext_gmac>;
73	tx_delay = <0x30>;
74	rx_delay = <0x10>;
75
76};
77