1XILINX AXI ETHERNET Device Tree Bindings
2--------------------------------------------------------
3
4Also called  AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core
5provides connectivity to an external ethernet PHY supporting different
6interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two
7segments of memory for buffering TX and RX, as well as the capability of
8offloading TX/RX checksum calculation off the processor.
9
10Management configuration is done through the AXI interface, while payload is
11sent and received through means of an AXI DMA controller. This driver
12includes the DMA driver code, so this driver is incompatible with AXI DMA
13driver.
14
15For more details about mdio please refer phy.txt file in the same directory.
16
17Required properties:
18- compatible	: Must be one of "xlnx,axi-ethernet-1.00.a",
19		  "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a"
20- reg		: Address and length of the IO space, as well as the address
21                  and length of the AXI DMA controller IO space, unless
22                  axistream-connected is specified, in which case the reg
23                  attribute of the node referenced by it is used.
24- interrupts	: Should be a list of 2 or 3 interrupts: TX DMA, RX DMA,
25		  and optionally Ethernet core. If axistream-connected is
26		  specified, the TX/RX DMA interrupts should be on that node
27		  instead, and only the Ethernet core interrupt is optionally
28		  specified here.
29- phy-handle	: Should point to the external phy device if exists. Pointing
30		  this to the PCS/PMA PHY is deprecated and should be avoided.
31		  See ethernet.txt file in the same directory.
32- xlnx,rxmem	: Set to allocated memory buffer for Rx/Tx in the hardware
33
34Optional properties:
35- phy-mode	: See ethernet.txt
36- xlnx,phy-type	: Deprecated, do not use, but still accepted in preference
37		  to phy-mode.
38- xlnx,txcsum	: 0 or empty for disabling TX checksum offload,
39		  1 to enable partial TX checksum offload,
40		  2 to enable full TX checksum offload
41- xlnx,rxcsum	: Same values as xlnx,txcsum but for RX checksum offload
42- xlnx,switch-x-sgmii : Boolean to indicate the Ethernet core is configured to
43		  support both 1000BaseX and SGMII modes. If set, the phy-mode
44		  should be set to match the mode selected on core reset (i.e.
45		  by the basex_or_sgmii core input line).
46- clock-names: 	  Tuple listing input clock names. Possible clocks:
47		  s_axi_lite_clk: Clock for AXI register slave interface
48		  axis_clk: AXI4-Stream clock for TXD RXD TXC and RXS interfaces
49		  ref_clk: Ethernet reference clock, used by signal delay
50			   primitives and transceivers
51		  mgt_clk: MGT reference clock (used by optional internal
52			   PCS/PMA PHY)
53
54		  Note that if s_axi_lite_clk is not specified by name, the
55		  first clock of any name is used for this. If that is also not
56		  specified, the clock rate is auto-detected from the CPU clock
57		  (but only on platforms where this is possible). New device
58		  trees should specify all applicable clocks by name - the
59		  fallbacks to an unnamed clock or to CPU clock are only for
60		  backward compatibility.
61- clocks: 	  Phandles to input clocks matching clock-names. Refer to common
62		  clock bindings.
63- axistream-connected: Reference to another node which contains the resources
64		       for the AXI DMA controller used by this device.
65		       If this is specified, the DMA-related resources from that
66		       device (DMA registers and DMA TX/RX interrupts) rather
67		       than this one will be used.
68 - mdio		: Child node for MDIO bus. Must be defined if PHY access is
69		  required through the core's MDIO interface (i.e. always,
70		  unless the PHY is accessed through a different bus).
71		  Non-standard MDIO bus frequency is supported via
72		  "clock-frequency", see mdio.yaml.
73
74 - pcs-handle: 	  Phandle to the internal PCS/PMA PHY in SGMII or 1000Base-X
75		  modes, where "pcs-handle" should be used to point
76		  to the PCS/PMA PHY, and "phy-handle" should point to an
77		  external PHY if exists.
78
79Example:
80	axi_ethernet_eth: ethernet@40c00000 {
81		compatible = "xlnx,axi-ethernet-1.00.a";
82		device_type = "network";
83		interrupt-parent = <&microblaze_0_axi_intc>;
84		interrupts = <2 0 1>;
85		clock-names = "s_axi_lite_clk", "axis_clk", "ref_clk", "mgt_clk";
86		clocks = <&axi_clk>, <&axi_clk>, <&pl_enet_ref_clk>, <&mgt_clk>;
87		phy-mode = "mii";
88		reg = <0x40c00000 0x40000 0x50c00000 0x40000>;
89		xlnx,rxcsum = <0x2>;
90		xlnx,rxmem = <0x800>;
91		xlnx,txcsum = <0x2>;
92		phy-handle = <&phy0>;
93		axi_ethernetlite_0_mdio: mdio {
94			#address-cells = <1>;
95			#size-cells = <0>;
96			phy0: phy@0 {
97				device_type = "ethernet-phy";
98				reg = <1>;
99			};
100		};
101	};
102