1Faraday Technology FTPCI100 PCI Host Bridge
2
3This PCI bridge is found inside that Cortina Systems Gemini SoC platform and
4is a generic IP block from Faraday Technology. It exists in two variants:
5plain and dual PCI. The plain version embeds a cascading interrupt controller
6into the host bridge. The dual version routes the interrupts to the host
7chips interrupt controller.
8
9The host controller appear on the PCI bus with vendor ID 0x159b (Faraday
10Technology) and product ID 0x4321.
11
12Mandatory properties:
13
14- compatible: ranging from specific to generic, should be one of
15  "cortina,gemini-pci", "faraday,ftpci100"
16  "cortina,gemini-pci-dual", "faraday,ftpci100-dual"
17  "faraday,ftpci100"
18  "faraday,ftpci100-dual"
19- reg: memory base and size for the host bridge
20- #address-cells: set to <3>
21- #size-cells: set to <2>
22- #interrupt-cells: set to <1>
23- bus-range: set to <0x00 0xff>
24- device_type, set to "pci"
25- ranges: see pci.txt
26- interrupt-map-mask: see pci.txt
27- interrupt-map: see pci.txt
28- dma-ranges: three ranges for the inbound memory region. The ranges must
29  be aligned to a 1MB boundary, and may be 1MB, 2MB, 4MB, 8MB, 16MB, 32MB, 64MB,
30  128MB, 256MB, 512MB, 1GB or 2GB in size. The memory should be marked as
31  pre-fetchable.
32
33Optional properties:
34- clocks: when present, this should contain the peripheral clock (PCLK) and the
35  PCI clock (PCICLK). If these are not present, they are assumed to be
36  hard-wired enabled and always on. The PCI clock will be 33 or 66 MHz.
37- clock-names: when present, this should contain "PCLK" for the peripheral
38  clock and "PCICLK" for the PCI-side clock.
39
40Mandatory subnodes:
41- For "faraday,ftpci100" a node representing the interrupt-controller inside the
42  host bridge is mandatory. It has the following mandatory properties:
43  - interrupt: see interrupt-controller/interrupts.txt
44  - interrupt-controller: see interrupt-controller/interrupts.txt
45  - #address-cells: set to <0>
46  - #interrupt-cells: set to <1>
47
48I/O space considerations:
49
50The plain variant has 128MiB of non-prefetchable memory space, whereas the
51"dual" variant has 64MiB. Take this into account when describing the ranges.
52
53Interrupt map considerations:
54
55The "dual" variant will get INT A, B, C, D from the system interrupt controller
56and should point to respective interrupt in that controller in its
57interrupt-map.
58
59The code which is the only documentation of how the Faraday PCI (the non-dual
60variant) interrupts assigns the default interrupt mapping/swizzling has
61typically been like this, doing the swizzling on the interrupt controller side
62rather than in the interconnect:
63
64interrupt-map-mask = <0xf800 0 0 7>;
65interrupt-map =
66	<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
67	<0x4800 0 0 2 &pci_intc 1>,
68	<0x4800 0 0 3 &pci_intc 2>,
69	<0x4800 0 0 4 &pci_intc 3>,
70	<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
71	<0x5000 0 0 2 &pci_intc 2>,
72	<0x5000 0 0 3 &pci_intc 3>,
73	<0x5000 0 0 4 &pci_intc 0>,
74	<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
75	<0x5800 0 0 2 &pci_intc 3>,
76	<0x5800 0 0 3 &pci_intc 0>,
77	<0x5800 0 0 4 &pci_intc 1>,
78	<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
79	<0x6000 0 0 2 &pci_intc 0>,
80	<0x6000 0 0 3 &pci_intc 1>,
81	<0x6000 0 0 4 &pci_intc 2>;
82
83Example:
84
85pci@50000000 {
86	compatible = "cortina,gemini-pci", "faraday,ftpci100";
87	reg = <0x50000000 0x100>;
88	interrupts = <8 IRQ_TYPE_LEVEL_HIGH>, /* PCI A */
89			<26 IRQ_TYPE_LEVEL_HIGH>, /* PCI B */
90			<27 IRQ_TYPE_LEVEL_HIGH>, /* PCI C */
91			<28 IRQ_TYPE_LEVEL_HIGH>; /* PCI D */
92	#address-cells = <3>;
93	#size-cells = <2>;
94	#interrupt-cells = <1>;
95
96	bus-range = <0x00 0xff>;
97	ranges = /* 1MiB I/O space 0x50000000-0x500fffff */
98		 <0x01000000 0 0          0x50000000 0 0x00100000>,
99		 /* 128MiB non-prefetchable memory 0x58000000-0x5fffffff */
100		 <0x02000000 0 0x58000000 0x58000000 0 0x08000000>;
101
102	/* DMA ranges */
103	dma-ranges =
104	/* 128MiB at 0x00000000-0x07ffffff */
105	<0x02000000 0 0x00000000 0x00000000 0 0x08000000>,
106	/* 64MiB at 0x00000000-0x03ffffff */
107	<0x02000000 0 0x00000000 0x00000000 0 0x04000000>,
108	/* 64MiB at 0x00000000-0x03ffffff */
109	<0x02000000 0 0x00000000 0x00000000 0 0x04000000>;
110
111	interrupt-map-mask = <0xf800 0 0 7>;
112	interrupt-map =
113		<0x4800 0 0 1 &pci_intc 0>, /* Slot 9 */
114		<0x4800 0 0 2 &pci_intc 1>,
115		<0x4800 0 0 3 &pci_intc 2>,
116		<0x4800 0 0 4 &pci_intc 3>,
117		<0x5000 0 0 1 &pci_intc 1>, /* Slot 10 */
118		<0x5000 0 0 2 &pci_intc 2>,
119		<0x5000 0 0 3 &pci_intc 3>,
120		<0x5000 0 0 4 &pci_intc 0>,
121		<0x5800 0 0 1 &pci_intc 2>, /* Slot 11 */
122		<0x5800 0 0 2 &pci_intc 3>,
123		<0x5800 0 0 3 &pci_intc 0>,
124		<0x5800 0 0 4 &pci_intc 1>,
125		<0x6000 0 0 1 &pci_intc 3>, /* Slot 12 */
126		<0x6000 0 0 2 &pci_intc 0>,
127		<0x6000 0 0 3 &pci_intc 0>,
128		<0x6000 0 0 4 &pci_intc 0>;
129	pci_intc: interrupt-controller {
130		interrupt-parent = <&intcon>;
131		interrupt-controller;
132		#address-cells = <0>;
133		#interrupt-cells = <1>;
134	};
135};
136