1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mediatek-pcie-gen3.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Gen3 PCIe controller on MediaTek SoCs
8
9maintainers:
10  - Jianjun Wang <jianjun.wang@mediatek.com>
11
12description: |+
13  PCIe Gen3 MAC controller for MediaTek SoCs, it supports Gen3 speed
14  and compatible with Gen2, Gen1 speed.
15
16  This PCIe controller supports up to 256 MSI vectors, the MSI hardware
17  block diagram is as follows:
18
19                    +-----+
20                    | GIC |
21                    +-----+
22                       ^
23                       |
24                   port->irq
25                       |
26               +-+-+-+-+-+-+-+-+
27               |0|1|2|3|4|5|6|7| (PCIe intc)
28               +-+-+-+-+-+-+-+-+
29                ^ ^           ^
30                | |    ...    |
31        +-------+ +------+    +-----------+
32        |                |                |
33  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
34  |0|1|...|30|31|  |0|1|...|30|31|  |0|1|...|30|31| (MSI sets)
35  +-+-+---+--+--+  +-+-+---+--+--+  +-+-+---+--+--+
36   ^ ^      ^  ^    ^ ^      ^  ^    ^ ^      ^  ^
37   | |      |  |    | |      |  |    | |      |  |  (MSI vectors)
38   | |      |  |    | |      |  |    | |      |  |
39
40    (MSI SET0)       (MSI SET1)  ...   (MSI SET7)
41
42  With 256 MSI vectors supported, the MSI vectors are composed of 8 sets,
43  each set has its own address for MSI message, and supports 32 MSI vectors
44  to generate interrupt.
45
46allOf:
47  - $ref: /schemas/pci/pci-bus.yaml#
48
49properties:
50  compatible:
51    const: mediatek,mt8192-pcie
52
53  reg:
54    maxItems: 1
55
56  reg-names:
57    items:
58      - const: pcie-mac
59
60  interrupts:
61    maxItems: 1
62
63  ranges:
64    minItems: 1
65    maxItems: 8
66
67  resets:
68    minItems: 1
69    maxItems: 2
70
71  reset-names:
72    minItems: 1
73    maxItems: 2
74    items:
75      - const: phy
76      - const: mac
77
78  clocks:
79    maxItems: 6
80
81  clock-names:
82    items:
83      - const: pl_250m
84      - const: tl_26m
85      - const: tl_96m
86      - const: tl_32k
87      - const: peri_26m
88      - const: top_133m
89
90  assigned-clocks:
91    maxItems: 1
92
93  assigned-clock-parents:
94    maxItems: 1
95
96  phys:
97    maxItems: 1
98
99  '#interrupt-cells':
100    const: 1
101
102  interrupt-controller:
103    description: Interrupt controller node for handling legacy PCI interrupts.
104    type: object
105    properties:
106      '#address-cells':
107        const: 0
108      '#interrupt-cells':
109        const: 1
110      interrupt-controller: true
111
112    required:
113      - '#address-cells'
114      - '#interrupt-cells'
115      - interrupt-controller
116
117    additionalProperties: false
118
119required:
120  - compatible
121  - reg
122  - reg-names
123  - interrupts
124  - ranges
125  - clocks
126  - '#interrupt-cells'
127  - interrupt-controller
128
129unevaluatedProperties: false
130
131examples:
132  - |
133    #include <dt-bindings/interrupt-controller/arm-gic.h>
134    #include <dt-bindings/interrupt-controller/irq.h>
135
136    bus {
137        #address-cells = <2>;
138        #size-cells = <2>;
139
140        pcie: pcie@11230000 {
141            compatible = "mediatek,mt8192-pcie";
142            device_type = "pci";
143            #address-cells = <3>;
144            #size-cells = <2>;
145            reg = <0x00 0x11230000 0x00 0x4000>;
146            reg-names = "pcie-mac";
147            interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>;
148            bus-range = <0x00 0xff>;
149            ranges = <0x82000000 0x00 0x12000000 0x00
150                      0x12000000 0x00 0x1000000>;
151            clocks = <&infracfg 44>,
152                     <&infracfg 40>,
153                     <&infracfg 43>,
154                     <&infracfg 97>,
155                     <&infracfg 99>,
156                     <&infracfg 111>;
157            clock-names = "pl_250m", "tl_26m", "tl_96m",
158                          "tl_32k", "peri_26m", "top_133m";
159            assigned-clocks = <&topckgen 50>;
160            assigned-clock-parents = <&topckgen 91>;
161
162            phys = <&pciephy>;
163            phy-names = "pcie-phy";
164
165            resets = <&infracfg_rst 2>,
166                     <&infracfg_rst 3>;
167            reset-names = "phy", "mac";
168
169            #interrupt-cells = <1>;
170            interrupt-map-mask = <0 0 0 0x7>;
171            interrupt-map = <0 0 0 1 &pcie_intc 0>,
172                            <0 0 0 2 &pcie_intc 1>,
173                            <0 0 0 3 &pcie_intc 2>,
174                            <0 0 0 4 &pcie_intc 3>;
175            pcie_intc: interrupt-controller {
176                      #address-cells = <0>;
177                      #interrupt-cells = <1>;
178                      interrupt-controller;
179            };
180        };
181    };
182