1*b97ee269SEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*b97ee269SEmmanuel Vadot%YAML 1.2 3*b97ee269SEmmanuel Vadot--- 4*b97ee269SEmmanuel Vadot$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie-ep.yaml# 5*b97ee269SEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*b97ee269SEmmanuel Vadot 7*b97ee269SEmmanuel Vadottitle: NVIDIA Tegra194 (and later) PCIe Endpoint controller (Synopsys DesignWare Core based) 8*b97ee269SEmmanuel Vadot 9*b97ee269SEmmanuel Vadotmaintainers: 10*b97ee269SEmmanuel Vadot - Thierry Reding <thierry.reding@gmail.com> 11*b97ee269SEmmanuel Vadot - Jon Hunter <jonathanh@nvidia.com> 12*b97ee269SEmmanuel Vadot - Vidya Sagar <vidyas@nvidia.com> 13*b97ee269SEmmanuel Vadot 14*b97ee269SEmmanuel Vadotdescription: | 15*b97ee269SEmmanuel Vadot This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus 16*b97ee269SEmmanuel Vadot inherits all the common properties defined in snps,dw-pcie-ep.yaml. Some 17*b97ee269SEmmanuel Vadot of the controller instances are dual mode; they can work either in Root 18*b97ee269SEmmanuel Vadot Port mode or Endpoint mode but one at a time. 19*b97ee269SEmmanuel Vadot 20*b97ee269SEmmanuel Vadot On Tegra194, controllers C0, C4 and C5 support Endpoint mode. 21*b97ee269SEmmanuel Vadot On Tegra234, controllers C5, C6, C7 and C10 support Endpoint mode. 22*b97ee269SEmmanuel Vadot 23*b97ee269SEmmanuel Vadot Note: On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 24*b97ee269SEmmanuel Vadot operate in the Endpoint mode because of the way the platform is designed. 25*b97ee269SEmmanuel Vadot 26*b97ee269SEmmanuel Vadotproperties: 27*b97ee269SEmmanuel Vadot compatible: 28*b97ee269SEmmanuel Vadot enum: 29*b97ee269SEmmanuel Vadot - nvidia,tegra194-pcie-ep 30*b97ee269SEmmanuel Vadot - nvidia,tegra234-pcie-ep 31*b97ee269SEmmanuel Vadot 32*b97ee269SEmmanuel Vadot reg: 33*b97ee269SEmmanuel Vadot items: 34*b97ee269SEmmanuel Vadot - description: controller's application logic registers 35*b97ee269SEmmanuel Vadot - description: iATU and DMA registers. This is where the iATU (internal 36*b97ee269SEmmanuel Vadot Address Translation Unit) registers of the PCIe core are made 37*b97ee269SEmmanuel Vadot available for software access. 38*b97ee269SEmmanuel Vadot - description: aperture where the Root Port's own configuration 39*b97ee269SEmmanuel Vadot registers are available. 40*b97ee269SEmmanuel Vadot - description: aperture used to map the remote Root Complex address space 41*b97ee269SEmmanuel Vadot 42*b97ee269SEmmanuel Vadot reg-names: 43*b97ee269SEmmanuel Vadot items: 44*b97ee269SEmmanuel Vadot - const: appl 45*b97ee269SEmmanuel Vadot - const: atu_dma 46*b97ee269SEmmanuel Vadot - const: dbi 47*b97ee269SEmmanuel Vadot - const: addr_space 48*b97ee269SEmmanuel Vadot 49*b97ee269SEmmanuel Vadot interrupts: 50*b97ee269SEmmanuel Vadot items: 51*b97ee269SEmmanuel Vadot - description: controller interrupt 52*b97ee269SEmmanuel Vadot 53*b97ee269SEmmanuel Vadot interrupt-names: 54*b97ee269SEmmanuel Vadot items: 55*b97ee269SEmmanuel Vadot - const: intr 56*b97ee269SEmmanuel Vadot 57*b97ee269SEmmanuel Vadot clocks: 58*b97ee269SEmmanuel Vadot items: 59*b97ee269SEmmanuel Vadot - description: module clock 60*b97ee269SEmmanuel Vadot 61*b97ee269SEmmanuel Vadot clock-names: 62*b97ee269SEmmanuel Vadot items: 63*b97ee269SEmmanuel Vadot - const: core 64*b97ee269SEmmanuel Vadot 65*b97ee269SEmmanuel Vadot resets: 66*b97ee269SEmmanuel Vadot items: 67*b97ee269SEmmanuel Vadot - description: APB bus interface reset 68*b97ee269SEmmanuel Vadot - description: module reset 69*b97ee269SEmmanuel Vadot 70*b97ee269SEmmanuel Vadot reset-names: 71*b97ee269SEmmanuel Vadot items: 72*b97ee269SEmmanuel Vadot - const: apb 73*b97ee269SEmmanuel Vadot - const: core 74*b97ee269SEmmanuel Vadot 75*b97ee269SEmmanuel Vadot reset-gpios: 76*b97ee269SEmmanuel Vadot description: Must contain a phandle to a GPIO controller followed by GPIO 77*b97ee269SEmmanuel Vadot that is being used as PERST input signal. Please refer to pci.txt. 78*b97ee269SEmmanuel Vadot 79*b97ee269SEmmanuel Vadot phys: 80*b97ee269SEmmanuel Vadot minItems: 1 81*b97ee269SEmmanuel Vadot maxItems: 8 82*b97ee269SEmmanuel Vadot 83*b97ee269SEmmanuel Vadot phy-names: 84*b97ee269SEmmanuel Vadot minItems: 1 85*b97ee269SEmmanuel Vadot items: 86*b97ee269SEmmanuel Vadot - const: p2u-0 87*b97ee269SEmmanuel Vadot - const: p2u-1 88*b97ee269SEmmanuel Vadot - const: p2u-2 89*b97ee269SEmmanuel Vadot - const: p2u-3 90*b97ee269SEmmanuel Vadot - const: p2u-4 91*b97ee269SEmmanuel Vadot - const: p2u-5 92*b97ee269SEmmanuel Vadot - const: p2u-6 93*b97ee269SEmmanuel Vadot - const: p2u-7 94*b97ee269SEmmanuel Vadot 95*b97ee269SEmmanuel Vadot power-domains: 96*b97ee269SEmmanuel Vadot maxItems: 1 97*b97ee269SEmmanuel Vadot description: | 98*b97ee269SEmmanuel Vadot A phandle to the node that controls power to the respective PCIe 99*b97ee269SEmmanuel Vadot controller and a specifier name for the PCIe controller. 100*b97ee269SEmmanuel Vadot 101*b97ee269SEmmanuel Vadot Tegra194 specifiers are defined in "include/dt-bindings/power/tegra194-powergate.h" 102*b97ee269SEmmanuel Vadot Tegra234 specifiers are defined in "include/dt-bindings/power/tegra234-powergate.h" 103*b97ee269SEmmanuel Vadot 104*b97ee269SEmmanuel Vadot interconnects: 105*b97ee269SEmmanuel Vadot items: 106*b97ee269SEmmanuel Vadot - description: memory read client 107*b97ee269SEmmanuel Vadot - description: memory write client 108*b97ee269SEmmanuel Vadot 109*b97ee269SEmmanuel Vadot interconnect-names: 110*b97ee269SEmmanuel Vadot items: 111*b97ee269SEmmanuel Vadot - const: dma-mem # read 112*b97ee269SEmmanuel Vadot - const: write 113*b97ee269SEmmanuel Vadot 114*b97ee269SEmmanuel Vadot dma-coherent: true 115*b97ee269SEmmanuel Vadot 116*b97ee269SEmmanuel Vadot nvidia,bpmp: 117*b97ee269SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle-array 118*b97ee269SEmmanuel Vadot description: | 119*b97ee269SEmmanuel Vadot Must contain a pair of phandles to BPMP controller node followed by 120*b97ee269SEmmanuel Vadot controller ID. Following are the controller IDs for each controller: 121*b97ee269SEmmanuel Vadot 122*b97ee269SEmmanuel Vadot Tegra194 123*b97ee269SEmmanuel Vadot 124*b97ee269SEmmanuel Vadot 0: C0 125*b97ee269SEmmanuel Vadot 1: C1 126*b97ee269SEmmanuel Vadot 2: C2 127*b97ee269SEmmanuel Vadot 3: C3 128*b97ee269SEmmanuel Vadot 4: C4 129*b97ee269SEmmanuel Vadot 5: C5 130*b97ee269SEmmanuel Vadot 131*b97ee269SEmmanuel Vadot Tegra234 132*b97ee269SEmmanuel Vadot 133*b97ee269SEmmanuel Vadot 0 : C0 134*b97ee269SEmmanuel Vadot 1 : C1 135*b97ee269SEmmanuel Vadot 2 : C2 136*b97ee269SEmmanuel Vadot 3 : C3 137*b97ee269SEmmanuel Vadot 4 : C4 138*b97ee269SEmmanuel Vadot 5 : C5 139*b97ee269SEmmanuel Vadot 6 : C6 140*b97ee269SEmmanuel Vadot 7 : C7 141*b97ee269SEmmanuel Vadot 8 : C8 142*b97ee269SEmmanuel Vadot 9 : C9 143*b97ee269SEmmanuel Vadot 10: C10 144*b97ee269SEmmanuel Vadot 145*b97ee269SEmmanuel Vadot items: 146*b97ee269SEmmanuel Vadot - items: 147*b97ee269SEmmanuel Vadot - description: phandle to BPMP controller node 148*b97ee269SEmmanuel Vadot - description: PCIe controller ID 149*b97ee269SEmmanuel Vadot maximum: 10 150*b97ee269SEmmanuel Vadot 151*b97ee269SEmmanuel Vadot nvidia,aspm-cmrt-us: 152*b97ee269SEmmanuel Vadot description: Common Mode Restore Time for proper operation of ASPM to be 153*b97ee269SEmmanuel Vadot specified in microseconds 154*b97ee269SEmmanuel Vadot 155*b97ee269SEmmanuel Vadot nvidia,aspm-pwr-on-t-us: 156*b97ee269SEmmanuel Vadot description: Power On time for proper operation of ASPM to be specified in 157*b97ee269SEmmanuel Vadot microseconds 158*b97ee269SEmmanuel Vadot 159*b97ee269SEmmanuel Vadot nvidia,aspm-l0s-entrance-latency-us: 160*b97ee269SEmmanuel Vadot description: ASPM L0s entrance latency to be specified in microseconds 161*b97ee269SEmmanuel Vadot 162*b97ee269SEmmanuel Vadot vddio-pex-ctl-supply: 163*b97ee269SEmmanuel Vadot description: A phandle to the regulator supply for PCIe side band signals 164*b97ee269SEmmanuel Vadot 165*b97ee269SEmmanuel Vadot nvidia,refclk-select-gpios: 166*b97ee269SEmmanuel Vadot maxItems: 1 167*b97ee269SEmmanuel Vadot description: GPIO used to enable REFCLK to controller from the host 168*b97ee269SEmmanuel Vadot 169*b97ee269SEmmanuel Vadot nvidia,enable-ext-refclk: 170*b97ee269SEmmanuel Vadot description: | 171*b97ee269SEmmanuel Vadot This boolean property needs to be present if the controller is configured 172*b97ee269SEmmanuel Vadot to receive Reference Clock from the host. 173*b97ee269SEmmanuel Vadot NOTE: This is applicable only for Tegra234. 174*b97ee269SEmmanuel Vadot 175*b97ee269SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 176*b97ee269SEmmanuel Vadot 177*b97ee269SEmmanuel Vadot nvidia,enable-srns: 178*b97ee269SEmmanuel Vadot description: | 179*b97ee269SEmmanuel Vadot This boolean property needs to be present if the controller is 180*b97ee269SEmmanuel Vadot configured to operate in SRNS (Separate Reference Clocks with No 181*b97ee269SEmmanuel Vadot Spread-Spectrum Clocking). NOTE: This is applicable only for 182*b97ee269SEmmanuel Vadot Tegra234. 183*b97ee269SEmmanuel Vadot 184*b97ee269SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/flag 185*b97ee269SEmmanuel Vadot 186*b97ee269SEmmanuel VadotallOf: 187*b97ee269SEmmanuel Vadot - $ref: /schemas/pci/snps,dw-pcie-ep.yaml# 188*b97ee269SEmmanuel Vadot 189*b97ee269SEmmanuel VadotunevaluatedProperties: false 190*b97ee269SEmmanuel Vadot 191*b97ee269SEmmanuel Vadotrequired: 192*b97ee269SEmmanuel Vadot - interrupts 193*b97ee269SEmmanuel Vadot - interrupt-names 194*b97ee269SEmmanuel Vadot - clocks 195*b97ee269SEmmanuel Vadot - clock-names 196*b97ee269SEmmanuel Vadot - resets 197*b97ee269SEmmanuel Vadot - reset-names 198*b97ee269SEmmanuel Vadot - power-domains 199*b97ee269SEmmanuel Vadot - reset-gpios 200*b97ee269SEmmanuel Vadot - vddio-pex-ctl-supply 201*b97ee269SEmmanuel Vadot - num-lanes 202*b97ee269SEmmanuel Vadot - phys 203*b97ee269SEmmanuel Vadot - phy-names 204*b97ee269SEmmanuel Vadot - nvidia,bpmp 205*b97ee269SEmmanuel Vadot 206*b97ee269SEmmanuel Vadotexamples: 207*b97ee269SEmmanuel Vadot - | 208*b97ee269SEmmanuel Vadot #include <dt-bindings/clock/tegra194-clock.h> 209*b97ee269SEmmanuel Vadot #include <dt-bindings/gpio/tegra194-gpio.h> 210*b97ee269SEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 211*b97ee269SEmmanuel Vadot #include <dt-bindings/power/tegra194-powergate.h> 212*b97ee269SEmmanuel Vadot #include <dt-bindings/reset/tegra194-reset.h> 213*b97ee269SEmmanuel Vadot 214*b97ee269SEmmanuel Vadot bus@0 { 215*b97ee269SEmmanuel Vadot #address-cells = <2>; 216*b97ee269SEmmanuel Vadot #size-cells = <2>; 217*b97ee269SEmmanuel Vadot ranges = <0x0 0x0 0x0 0x8 0x0>; 218*b97ee269SEmmanuel Vadot 219*b97ee269SEmmanuel Vadot pcie-ep@141a0000 { 220*b97ee269SEmmanuel Vadot compatible = "nvidia,tegra194-pcie-ep"; 221*b97ee269SEmmanuel Vadot reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 222*b97ee269SEmmanuel Vadot <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 223*b97ee269SEmmanuel Vadot <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 224*b97ee269SEmmanuel Vadot <0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 225*b97ee269SEmmanuel Vadot reg-names = "appl", "atu_dma", "dbi", "addr_space"; 226*b97ee269SEmmanuel Vadot interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 227*b97ee269SEmmanuel Vadot interrupt-names = "intr"; 228*b97ee269SEmmanuel Vadot 229*b97ee269SEmmanuel Vadot clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 230*b97ee269SEmmanuel Vadot clock-names = "core"; 231*b97ee269SEmmanuel Vadot 232*b97ee269SEmmanuel Vadot resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 233*b97ee269SEmmanuel Vadot <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 234*b97ee269SEmmanuel Vadot reset-names = "apb", "core"; 235*b97ee269SEmmanuel Vadot 236*b97ee269SEmmanuel Vadot power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 237*b97ee269SEmmanuel Vadot pinctrl-names = "default"; 238*b97ee269SEmmanuel Vadot pinctrl-0 = <&clkreq_c5_bi_dir_state>; 239*b97ee269SEmmanuel Vadot 240*b97ee269SEmmanuel Vadot nvidia,bpmp = <&bpmp 5>; 241*b97ee269SEmmanuel Vadot 242*b97ee269SEmmanuel Vadot nvidia,aspm-cmrt-us = <60>; 243*b97ee269SEmmanuel Vadot nvidia,aspm-pwr-on-t-us = <20>; 244*b97ee269SEmmanuel Vadot nvidia,aspm-l0s-entrance-latency-us = <3>; 245*b97ee269SEmmanuel Vadot 246*b97ee269SEmmanuel Vadot vddio-pex-ctl-supply = <&vdd_1v8ao>; 247*b97ee269SEmmanuel Vadot 248*b97ee269SEmmanuel Vadot reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 249*b97ee269SEmmanuel Vadot 250*b97ee269SEmmanuel Vadot nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 251*b97ee269SEmmanuel Vadot GPIO_ACTIVE_HIGH>; 252*b97ee269SEmmanuel Vadot 253*b97ee269SEmmanuel Vadot num-lanes = <8>; 254*b97ee269SEmmanuel Vadot 255*b97ee269SEmmanuel Vadot phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 256*b97ee269SEmmanuel Vadot <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 257*b97ee269SEmmanuel Vadot <&p2u_nvhs_6>, <&p2u_nvhs_7>; 258*b97ee269SEmmanuel Vadot 259*b97ee269SEmmanuel Vadot phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 260*b97ee269SEmmanuel Vadot "p2u-5", "p2u-6", "p2u-7"; 261*b97ee269SEmmanuel Vadot }; 262*b97ee269SEmmanuel Vadot }; 263*b97ee269SEmmanuel Vadot 264*b97ee269SEmmanuel Vadot - | 265*b97ee269SEmmanuel Vadot #include <dt-bindings/clock/tegra234-clock.h> 266*b97ee269SEmmanuel Vadot #include <dt-bindings/gpio/tegra234-gpio.h> 267*b97ee269SEmmanuel Vadot #include <dt-bindings/interrupt-controller/arm-gic.h> 268*b97ee269SEmmanuel Vadot #include <dt-bindings/power/tegra234-powergate.h> 269*b97ee269SEmmanuel Vadot #include <dt-bindings/reset/tegra234-reset.h> 270*b97ee269SEmmanuel Vadot 271*b97ee269SEmmanuel Vadot bus@0 { 272*b97ee269SEmmanuel Vadot #address-cells = <2>; 273*b97ee269SEmmanuel Vadot #size-cells = <2>; 274*b97ee269SEmmanuel Vadot ranges = <0x0 0x0 0x0 0x8 0x0>; 275*b97ee269SEmmanuel Vadot 276*b97ee269SEmmanuel Vadot pcie-ep@141a0000 { 277*b97ee269SEmmanuel Vadot compatible = "nvidia,tegra234-pcie-ep"; 278*b97ee269SEmmanuel Vadot power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX8A>; 279*b97ee269SEmmanuel Vadot reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */ 280*b97ee269SEmmanuel Vadot <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */ 281*b97ee269SEmmanuel Vadot <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */ 282*b97ee269SEmmanuel Vadot <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */ 283*b97ee269SEmmanuel Vadot reg-names = "appl", "atu_dma", "dbi", "addr_space"; 284*b97ee269SEmmanuel Vadot 285*b97ee269SEmmanuel Vadot interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 286*b97ee269SEmmanuel Vadot interrupt-names = "intr"; 287*b97ee269SEmmanuel Vadot 288*b97ee269SEmmanuel Vadot clocks = <&bpmp TEGRA234_CLK_PEX1_C5_CORE>; 289*b97ee269SEmmanuel Vadot clock-names = "core"; 290*b97ee269SEmmanuel Vadot 291*b97ee269SEmmanuel Vadot resets = <&bpmp TEGRA234_RESET_PEX1_CORE_5_APB>, 292*b97ee269SEmmanuel Vadot <&bpmp TEGRA234_RESET_PEX1_CORE_5>; 293*b97ee269SEmmanuel Vadot reset-names = "apb", "core"; 294*b97ee269SEmmanuel Vadot 295*b97ee269SEmmanuel Vadot nvidia,bpmp = <&bpmp 5>; 296*b97ee269SEmmanuel Vadot 297*b97ee269SEmmanuel Vadot nvidia,enable-ext-refclk; 298*b97ee269SEmmanuel Vadot nvidia,aspm-cmrt-us = <60>; 299*b97ee269SEmmanuel Vadot nvidia,aspm-pwr-on-t-us = <20>; 300*b97ee269SEmmanuel Vadot nvidia,aspm-l0s-entrance-latency-us = <3>; 301*b97ee269SEmmanuel Vadot 302*b97ee269SEmmanuel Vadot vddio-pex-ctl-supply = <&p3701_vdd_1v8_ls>; 303*b97ee269SEmmanuel Vadot 304*b97ee269SEmmanuel Vadot reset-gpios = <&gpio TEGRA234_MAIN_GPIO(AF, 1) GPIO_ACTIVE_LOW>; 305*b97ee269SEmmanuel Vadot 306*b97ee269SEmmanuel Vadot nvidia,refclk-select-gpios = <&gpio_aon 307*b97ee269SEmmanuel Vadot TEGRA234_AON_GPIO(AA, 4) 308*b97ee269SEmmanuel Vadot GPIO_ACTIVE_HIGH>; 309*b97ee269SEmmanuel Vadot 310*b97ee269SEmmanuel Vadot num-lanes = <8>; 311*b97ee269SEmmanuel Vadot 312*b97ee269SEmmanuel Vadot phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 313*b97ee269SEmmanuel Vadot <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 314*b97ee269SEmmanuel Vadot <&p2u_nvhs_6>, <&p2u_nvhs_7>; 315*b97ee269SEmmanuel Vadot 316*b97ee269SEmmanuel Vadot phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 317*b97ee269SEmmanuel Vadot "p2u-5", "p2u-6", "p2u-7"; 318*b97ee269SEmmanuel Vadot }; 319*b97ee269SEmmanuel Vadot }; 320