1c66ec88fSEmmanuel VadotNVIDIA Tegra PCIe controller (Synopsys DesignWare Core based) 2c66ec88fSEmmanuel Vadot 3c66ec88fSEmmanuel VadotThis PCIe controller is based on the Synopsis Designware PCIe IP 4354d7675SEmmanuel Vadotand thus inherits all the common properties defined in snps,dw-pcie.yaml and 5354d7675SEmmanuel Vadotsnps,dw-pcie-ep.yaml. 6c66ec88fSEmmanuel VadotSome of the controller instances are dual mode where in they can work either 7c66ec88fSEmmanuel Vadotin root port mode or endpoint mode but one at a time. 8c66ec88fSEmmanuel Vadot 9c66ec88fSEmmanuel VadotRequired properties: 10c66ec88fSEmmanuel Vadot- power-domains: A phandle to the node that controls power to the respective 11c66ec88fSEmmanuel Vadot PCIe controller and a specifier name for the PCIe controller. Following are 12c66ec88fSEmmanuel Vadot the specifiers for the different PCIe controllers 13c66ec88fSEmmanuel Vadot TEGRA194_POWER_DOMAIN_PCIEX8B: C0 14c66ec88fSEmmanuel Vadot TEGRA194_POWER_DOMAIN_PCIEX1A: C1 15c66ec88fSEmmanuel Vadot TEGRA194_POWER_DOMAIN_PCIEX1A: C2 16c66ec88fSEmmanuel Vadot TEGRA194_POWER_DOMAIN_PCIEX1A: C3 17c66ec88fSEmmanuel Vadot TEGRA194_POWER_DOMAIN_PCIEX4A: C4 18c66ec88fSEmmanuel Vadot TEGRA194_POWER_DOMAIN_PCIEX8A: C5 19c66ec88fSEmmanuel Vadot these specifiers are defined in 20c66ec88fSEmmanuel Vadot "include/dt-bindings/power/tegra194-powergate.h" file. 21c66ec88fSEmmanuel Vadot- reg: A list of physical base address and length pairs for each set of 22c66ec88fSEmmanuel Vadot controller registers. Must contain an entry for each entry in the reg-names 23c66ec88fSEmmanuel Vadot property. 24c66ec88fSEmmanuel Vadot- reg-names: Must include the following entries: 25c66ec88fSEmmanuel Vadot "appl": Controller's application logic registers 26354d7675SEmmanuel Vadot "config": As per the definition in snps,dw-pcie.yaml 27c66ec88fSEmmanuel Vadot "atu_dma": iATU and DMA registers. This is where the iATU (internal Address 28c66ec88fSEmmanuel Vadot Translation Unit) registers of the PCIe core are made available 29c66ec88fSEmmanuel Vadot for SW access. 30c66ec88fSEmmanuel Vadot "dbi": The aperture where root port's own configuration registers are 31c66ec88fSEmmanuel Vadot available 32c66ec88fSEmmanuel Vadot- interrupts: A list of interrupt outputs of the controller. Must contain an 33c66ec88fSEmmanuel Vadot entry for each entry in the interrupt-names property. 34c66ec88fSEmmanuel Vadot- interrupt-names: Must include the following entries: 35c66ec88fSEmmanuel Vadot "intr": The Tegra interrupt that is asserted for controller interrupts 36c66ec88fSEmmanuel Vadot- clocks: Must contain an entry for each entry in clock-names. 37c66ec88fSEmmanuel Vadot See ../clocks/clock-bindings.txt for details. 38c66ec88fSEmmanuel Vadot- clock-names: Must include the following entries: 39c66ec88fSEmmanuel Vadot - core 40c66ec88fSEmmanuel Vadot- resets: Must contain an entry for each entry in reset-names. 41c66ec88fSEmmanuel Vadot See ../reset/reset.txt for details. 42c66ec88fSEmmanuel Vadot- reset-names: Must include the following entries: 43c66ec88fSEmmanuel Vadot - apb 44c66ec88fSEmmanuel Vadot - core 45c66ec88fSEmmanuel Vadot- phys: Must contain a phandle to P2U PHY for each entry in phy-names. 46c66ec88fSEmmanuel Vadot- phy-names: Must include an entry for each active lane. 47c66ec88fSEmmanuel Vadot "p2u-N": where N ranges from 0 to one less than the total number of lanes 48c66ec88fSEmmanuel Vadot- nvidia,bpmp: Must contain a pair of phandle to BPMP controller node followed 49c66ec88fSEmmanuel Vadot by controller-id. Following are the controller ids for each controller. 50c66ec88fSEmmanuel Vadot 0: C0 51c66ec88fSEmmanuel Vadot 1: C1 52c66ec88fSEmmanuel Vadot 2: C2 53c66ec88fSEmmanuel Vadot 3: C3 54c66ec88fSEmmanuel Vadot 4: C4 55c66ec88fSEmmanuel Vadot 5: C5 56c66ec88fSEmmanuel Vadot- vddio-pex-ctl-supply: Regulator supply for PCIe side band signals 57c66ec88fSEmmanuel Vadot 58c66ec88fSEmmanuel VadotRC mode: 59c66ec88fSEmmanuel Vadot- compatible: Tegra19x must contain "nvidia,tegra194-pcie" 60c66ec88fSEmmanuel Vadot- device_type: Must be "pci" for RC mode 61c66ec88fSEmmanuel Vadot- interrupt-names: Must include the following entries: 62c66ec88fSEmmanuel Vadot "msi": The Tegra interrupt that is asserted when an MSI is received 63c66ec88fSEmmanuel Vadot- bus-range: Range of bus numbers associated with this controller 64c66ec88fSEmmanuel Vadot- #address-cells: Address representation for root ports (must be 3) 65c66ec88fSEmmanuel Vadot - cell 0 specifies the bus and device numbers of the root port: 66c66ec88fSEmmanuel Vadot [23:16]: bus number 67c66ec88fSEmmanuel Vadot [15:11]: device number 68c66ec88fSEmmanuel Vadot - cell 1 denotes the upper 32 address bits and should be 0 69c66ec88fSEmmanuel Vadot - cell 2 contains the lower 32 address bits and is used to translate to the 70c66ec88fSEmmanuel Vadot CPU address space 71c66ec88fSEmmanuel Vadot- #size-cells: Size representation for root ports (must be 2) 72c66ec88fSEmmanuel Vadot- ranges: Describes the translation of addresses for root ports and standard 73c66ec88fSEmmanuel Vadot PCI regions. The entries must be 7 cells each, where the first three cells 74c66ec88fSEmmanuel Vadot correspond to the address as described for the #address-cells property 75c66ec88fSEmmanuel Vadot above, the fourth and fifth cells are for the physical CPU address to 76c66ec88fSEmmanuel Vadot translate to and the sixth and seventh cells are as described for the 77c66ec88fSEmmanuel Vadot #size-cells property above. 78c66ec88fSEmmanuel Vadot - Entries setup the mapping for the standard I/O, memory and 79c66ec88fSEmmanuel Vadot prefetchable PCI regions. The first cell determines the type of region 80c66ec88fSEmmanuel Vadot that is setup: 81c66ec88fSEmmanuel Vadot - 0x81000000: I/O memory region 82c66ec88fSEmmanuel Vadot - 0x82000000: non-prefetchable memory region 83c66ec88fSEmmanuel Vadot - 0xc2000000: prefetchable memory region 84c66ec88fSEmmanuel Vadot Please refer to the standard PCI bus binding document for a more detailed 85c66ec88fSEmmanuel Vadot explanation. 86c66ec88fSEmmanuel Vadot- #interrupt-cells: Size representation for interrupts (must be 1) 87c66ec88fSEmmanuel Vadot- interrupt-map-mask and interrupt-map: Standard PCI IRQ mapping properties 88c66ec88fSEmmanuel Vadot Please refer to the standard PCI bus binding document for a more detailed 89c66ec88fSEmmanuel Vadot explanation. 90c66ec88fSEmmanuel Vadot 91c66ec88fSEmmanuel VadotEP mode: 92c66ec88fSEmmanuel VadotIn Tegra194, Only controllers C0, C4 & C5 support EP mode. 93c66ec88fSEmmanuel Vadot- compatible: Tegra19x must contain "nvidia,tegra194-pcie-ep" 94c66ec88fSEmmanuel Vadot- reg-names: Must include the following entries: 95c66ec88fSEmmanuel Vadot "addr_space": Used to map remote RC address space 96c66ec88fSEmmanuel Vadot- reset-gpios: Must contain a phandle to a GPIO controller followed by 97c66ec88fSEmmanuel Vadot GPIO that is being used as PERST input signal. Please refer to pci.txt 98c66ec88fSEmmanuel Vadot document. 99c66ec88fSEmmanuel Vadot 100c66ec88fSEmmanuel VadotOptional properties: 101c66ec88fSEmmanuel Vadot- pinctrl-names: A list of pinctrl state names. 102c66ec88fSEmmanuel Vadot It is mandatory for C5 controller and optional for other controllers. 103c66ec88fSEmmanuel Vadot - "default": Configures PCIe I/O for proper operation. 104c66ec88fSEmmanuel Vadot- pinctrl-0: phandle for the 'default' state of pin configuration. 105c66ec88fSEmmanuel Vadot It is mandatory for C5 controller and optional for other controllers. 106c66ec88fSEmmanuel Vadot- supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt 107c66ec88fSEmmanuel Vadot- nvidia,update-fc-fixup: This is a boolean property and needs to be present to 108c66ec88fSEmmanuel Vadot improve performance when a platform is designed in such a way that it 109c66ec88fSEmmanuel Vadot satisfies at least one of the following conditions thereby enabling root 110c66ec88fSEmmanuel Vadot port to exchange optimum number of FC (Flow Control) credits with 111c66ec88fSEmmanuel Vadot downstream devices 112c66ec88fSEmmanuel Vadot 1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS) 113c66ec88fSEmmanuel Vadot 2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and 114c66ec88fSEmmanuel Vadot a) speed is Gen-2 and MPS is 256B 115c66ec88fSEmmanuel Vadot b) speed is >= Gen-3 with any MPS 116c66ec88fSEmmanuel Vadot- nvidia,aspm-cmrt-us: Common Mode Restore Time for proper operation of ASPM 117c66ec88fSEmmanuel Vadot to be specified in microseconds 118c66ec88fSEmmanuel Vadot- nvidia,aspm-pwr-on-t-us: Power On time for proper operation of ASPM to be 119c66ec88fSEmmanuel Vadot specified in microseconds 120c66ec88fSEmmanuel Vadot- nvidia,aspm-l0s-entrance-latency-us: ASPM L0s entrance latency to be 121c66ec88fSEmmanuel Vadot specified in microseconds 122c66ec88fSEmmanuel Vadot 123c66ec88fSEmmanuel VadotRC mode: 124c66ec88fSEmmanuel Vadot- vpcie3v3-supply: A phandle to the regulator node that supplies 3.3V to the slot 125c66ec88fSEmmanuel Vadot if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 126c66ec88fSEmmanuel Vadot in p2972-0000 platform). 127c66ec88fSEmmanuel Vadot- vpcie12v-supply: A phandle to the regulator node that supplies 12V to the slot 128c66ec88fSEmmanuel Vadot if the platform has one such slot. (Ex:- x16 slot owned by C5 controller 129c66ec88fSEmmanuel Vadot in p2972-0000 platform). 130c66ec88fSEmmanuel Vadot 131c66ec88fSEmmanuel VadotEP mode: 132c66ec88fSEmmanuel Vadot- nvidia,refclk-select-gpios: Must contain a phandle to a GPIO controller 133c66ec88fSEmmanuel Vadot followed by GPIO that is being used to enable REFCLK to controller from host 134c66ec88fSEmmanuel Vadot 135c66ec88fSEmmanuel VadotNOTE:- On Tegra194's P2972-0000 platform, only C5 controller can be enabled to 136c66ec88fSEmmanuel Vadotoperate in the endpoint mode because of the way the platform is designed. 137c66ec88fSEmmanuel Vadot 138c66ec88fSEmmanuel VadotExamples: 139c66ec88fSEmmanuel Vadot========= 140c66ec88fSEmmanuel Vadot 141c66ec88fSEmmanuel VadotTegra194 RC mode: 142c66ec88fSEmmanuel Vadot----------------- 143c66ec88fSEmmanuel Vadot 144c66ec88fSEmmanuel Vadot pcie@14180000 { 145c66ec88fSEmmanuel Vadot compatible = "nvidia,tegra194-pcie"; 146c66ec88fSEmmanuel Vadot power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>; 147c66ec88fSEmmanuel Vadot reg = <0x00 0x14180000 0x0 0x00020000 /* appl registers (128K) */ 148c66ec88fSEmmanuel Vadot 0x00 0x38000000 0x0 0x00040000 /* configuration space (256K) */ 149c66ec88fSEmmanuel Vadot 0x00 0x38040000 0x0 0x00040000>; /* iATU_DMA reg space (256K) */ 150c66ec88fSEmmanuel Vadot reg-names = "appl", "config", "atu_dma"; 151c66ec88fSEmmanuel Vadot 152c66ec88fSEmmanuel Vadot #address-cells = <3>; 153c66ec88fSEmmanuel Vadot #size-cells = <2>; 154c66ec88fSEmmanuel Vadot device_type = "pci"; 155c66ec88fSEmmanuel Vadot num-lanes = <8>; 156c66ec88fSEmmanuel Vadot linux,pci-domain = <0>; 157c66ec88fSEmmanuel Vadot 158c66ec88fSEmmanuel Vadot pinctrl-names = "default"; 159c66ec88fSEmmanuel Vadot pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>; 160c66ec88fSEmmanuel Vadot 161c66ec88fSEmmanuel Vadot clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>; 162c66ec88fSEmmanuel Vadot clock-names = "core"; 163c66ec88fSEmmanuel Vadot 164c66ec88fSEmmanuel Vadot resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>, 165c66ec88fSEmmanuel Vadot <&bpmp TEGRA194_RESET_PEX0_CORE_0>; 166c66ec88fSEmmanuel Vadot reset-names = "apb", "core"; 167c66ec88fSEmmanuel Vadot 168c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ 169c66ec88fSEmmanuel Vadot <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ 170c66ec88fSEmmanuel Vadot interrupt-names = "intr", "msi"; 171c66ec88fSEmmanuel Vadot 172c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 173c66ec88fSEmmanuel Vadot interrupt-map-mask = <0 0 0 0>; 174c66ec88fSEmmanuel Vadot interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 175c66ec88fSEmmanuel Vadot 176c66ec88fSEmmanuel Vadot nvidia,bpmp = <&bpmp 0>; 177c66ec88fSEmmanuel Vadot 178c66ec88fSEmmanuel Vadot supports-clkreq; 179c66ec88fSEmmanuel Vadot nvidia,aspm-cmrt-us = <60>; 180c66ec88fSEmmanuel Vadot nvidia,aspm-pwr-on-t-us = <20>; 181c66ec88fSEmmanuel Vadot nvidia,aspm-l0s-entrance-latency-us = <3>; 182c66ec88fSEmmanuel Vadot 183c66ec88fSEmmanuel Vadot bus-range = <0x0 0xff>; 184c66ec88fSEmmanuel Vadot ranges = <0x81000000 0x0 0x38100000 0x0 0x38100000 0x0 0x00100000 /* downstream I/O (1MB) */ 185c66ec88fSEmmanuel Vadot 0x82000000 0x0 0x38200000 0x0 0x38200000 0x0 0x01E00000 /* non-prefetchable memory (30MB) */ 186c66ec88fSEmmanuel Vadot 0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory (16GB) */ 187c66ec88fSEmmanuel Vadot 188c66ec88fSEmmanuel Vadot vddio-pex-ctl-supply = <&vdd_1v8ao>; 189c66ec88fSEmmanuel Vadot vpcie3v3-supply = <&vdd_3v3_pcie>; 190c66ec88fSEmmanuel Vadot vpcie12v-supply = <&vdd_12v_pcie>; 191c66ec88fSEmmanuel Vadot 192c66ec88fSEmmanuel Vadot phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>, 193c66ec88fSEmmanuel Vadot <&p2u_hsio_5>; 194c66ec88fSEmmanuel Vadot phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3"; 195c66ec88fSEmmanuel Vadot }; 196c66ec88fSEmmanuel Vadot 197c66ec88fSEmmanuel VadotTegra194 EP mode: 198c66ec88fSEmmanuel Vadot----------------- 199c66ec88fSEmmanuel Vadot 200*8cc087a1SEmmanuel Vadot pcie-ep@141a0000 { 201c66ec88fSEmmanuel Vadot compatible = "nvidia,tegra194-pcie-ep", "snps,dw-pcie-ep"; 202c66ec88fSEmmanuel Vadot power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8A>; 203c66ec88fSEmmanuel Vadot reg = <0x00 0x141a0000 0x0 0x00020000 /* appl registers (128K) */ 204c66ec88fSEmmanuel Vadot 0x00 0x3a040000 0x0 0x00040000 /* iATU_DMA reg space (256K) */ 205c66ec88fSEmmanuel Vadot 0x00 0x3a080000 0x0 0x00040000 /* DBI reg space (256K) */ 206c66ec88fSEmmanuel Vadot 0x1c 0x00000000 0x4 0x00000000>; /* Address Space (16G) */ 207c66ec88fSEmmanuel Vadot reg-names = "appl", "atu_dma", "dbi", "addr_space"; 208c66ec88fSEmmanuel Vadot 209c66ec88fSEmmanuel Vadot num-lanes = <8>; 210c66ec88fSEmmanuel Vadot num-ib-windows = <2>; 211c66ec88fSEmmanuel Vadot num-ob-windows = <8>; 212c66ec88fSEmmanuel Vadot 213c66ec88fSEmmanuel Vadot pinctrl-names = "default"; 214c66ec88fSEmmanuel Vadot pinctrl-0 = <&clkreq_c5_bi_dir_state>; 215c66ec88fSEmmanuel Vadot 216c66ec88fSEmmanuel Vadot clocks = <&bpmp TEGRA194_CLK_PEX1_CORE_5>; 217c66ec88fSEmmanuel Vadot clock-names = "core"; 218c66ec88fSEmmanuel Vadot 219c66ec88fSEmmanuel Vadot resets = <&bpmp TEGRA194_RESET_PEX1_CORE_5_APB>, 220c66ec88fSEmmanuel Vadot <&bpmp TEGRA194_RESET_PEX1_CORE_5>; 221c66ec88fSEmmanuel Vadot reset-names = "apb", "core"; 222c66ec88fSEmmanuel Vadot 223c66ec88fSEmmanuel Vadot interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ 224c66ec88fSEmmanuel Vadot interrupt-names = "intr"; 225c66ec88fSEmmanuel Vadot 226c66ec88fSEmmanuel Vadot nvidia,bpmp = <&bpmp 5>; 227c66ec88fSEmmanuel Vadot 228c66ec88fSEmmanuel Vadot nvidia,aspm-cmrt-us = <60>; 229c66ec88fSEmmanuel Vadot nvidia,aspm-pwr-on-t-us = <20>; 230c66ec88fSEmmanuel Vadot nvidia,aspm-l0s-entrance-latency-us = <3>; 231c66ec88fSEmmanuel Vadot 232c66ec88fSEmmanuel Vadot vddio-pex-ctl-supply = <&vdd_1v8ao>; 233c66ec88fSEmmanuel Vadot 234c66ec88fSEmmanuel Vadot reset-gpios = <&gpio TEGRA194_MAIN_GPIO(GG, 1) GPIO_ACTIVE_LOW>; 235c66ec88fSEmmanuel Vadot 236c66ec88fSEmmanuel Vadot nvidia,refclk-select-gpios = <&gpio_aon TEGRA194_AON_GPIO(AA, 5) 237c66ec88fSEmmanuel Vadot GPIO_ACTIVE_HIGH>; 238c66ec88fSEmmanuel Vadot 239c66ec88fSEmmanuel Vadot phys = <&p2u_nvhs_0>, <&p2u_nvhs_1>, <&p2u_nvhs_2>, 240c66ec88fSEmmanuel Vadot <&p2u_nvhs_3>, <&p2u_nvhs_4>, <&p2u_nvhs_5>, 241c66ec88fSEmmanuel Vadot <&p2u_nvhs_6>, <&p2u_nvhs_7>; 242c66ec88fSEmmanuel Vadot 243c66ec88fSEmmanuel Vadot phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3", "p2u-4", 244c66ec88fSEmmanuel Vadot "p2u-5", "p2u-6", "p2u-7"; 245c66ec88fSEmmanuel Vadot }; 246