1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/nvidia,tegra194-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NVIDIA Tegra194 (and later) PCIe controller (Synopsys DesignWare Core based)
8
9maintainers:
10  - Thierry Reding <thierry.reding@gmail.com>
11  - Jon Hunter <jonathanh@nvidia.com>
12  - Vidya Sagar <vidyas@nvidia.com>
13
14description: |
15  This PCIe controller is based on the Synopsys DesignWare PCIe IP and thus
16  inherits all the common properties defined in snps,dw-pcie.yaml. Some of
17  the controller instances are dual mode where in they can work either in
18  Root Port mode or Endpoint mode but one at a time.
19
20  See nvidia,tegra194-pcie-ep.yaml for details on the Endpoint mode device
21  tree bindings.
22
23properties:
24  compatible:
25    enum:
26      - nvidia,tegra194-pcie
27      - nvidia,tegra234-pcie
28
29  reg:
30    minItems: 4
31    items:
32      - description: controller's application logic registers
33      - description: configuration registers
34      - description: iATU and DMA registers. This is where the iATU (internal
35          Address Translation Unit) registers of the PCIe core are made
36          available for software access.
37      - description: aperture where the Root Port's own configuration
38          registers are available.
39      - description: aperture to access the configuration space through ECAM.
40
41  reg-names:
42    minItems: 4
43    items:
44      - const: appl
45      - const: config
46      - const: atu_dma
47      - const: dbi
48      - const: ecam
49
50  interrupts:
51    items:
52      - description: controller interrupt
53      - description: MSI interrupt
54
55  interrupt-names:
56    items:
57      - const: intr
58      - const: msi
59
60  clocks:
61    items:
62      - description: module clock
63
64  clock-names:
65    items:
66      - const: core
67
68  resets:
69    items:
70      - description: APB bus interface reset
71      - description: module reset
72
73  reset-names:
74    items:
75      - const: apb
76      - const: core
77
78  phys:
79    minItems: 1
80    maxItems: 8
81
82  phy-names:
83    minItems: 1
84    items:
85      - const: p2u-0
86      - const: p2u-1
87      - const: p2u-2
88      - const: p2u-3
89      - const: p2u-4
90      - const: p2u-5
91      - const: p2u-6
92      - const: p2u-7
93
94  power-domains:
95    maxItems: 1
96    description: |
97      A phandle to the node that controls power to the respective PCIe
98      controller and a specifier name for the PCIe controller.
99
100      Tegra194 specifiers defined in "include/dt-bindings/power/tegra194-powergate.h"
101      Tegra234 specifiers defined in "include/dt-bindings/power/tegra234-powergate.h"
102
103  interconnects:
104    items:
105      - description: memory read client
106      - description: memory write client
107
108  interconnect-names:
109    items:
110      - const: dma-mem # read
111      - const: write
112
113  dma-coherent: true
114
115  nvidia,bpmp:
116    $ref: /schemas/types.yaml#/definitions/phandle-array
117    description: |
118      Must contain a pair of phandles to BPMP controller node followed by
119      controller ID. Following are the controller IDs for each controller:
120
121      Tegra194
122
123        0: C0
124        1: C1
125        2: C2
126        3: C3
127        4: C4
128        5: C5
129
130      Tegra234
131
132        0 : C0
133        1 : C1
134        2 : C2
135        3 : C3
136        4 : C4
137        5 : C5
138        6 : C6
139        7 : C7
140        8 : C8
141        9 : C9
142        10: C10
143
144    items:
145      - items:
146          - description: phandle to BPMP controller node
147          - description: PCIe controller ID
148            maximum: 10
149
150  nvidia,update-fc-fixup:
151    description: |
152      This is a boolean property and needs to be present to improve performance
153      when a platform is designed in such a way that it satisfies at least one
154      of the following conditions thereby enabling Root Port to exchange
155      optimum number of FC (Flow Control) credits with downstream devices:
156
157      NOTE: This is applicable only for Tegra194.
158
159        1. If C0/C4/C5 run at x1/x2 link widths (irrespective of speed and MPS)
160        2. If C0/C1/C2/C3/C4/C5 operate at their respective max link widths and
161          a) speed is Gen-2 and MPS is 256B
162          b) speed is >= Gen-3 with any MPS
163
164    $ref: /schemas/types.yaml#/definitions/flag
165
166  nvidia,aspm-cmrt-us:
167    description: Common Mode Restore Time for proper operation of ASPM to be
168      specified in microseconds
169
170  nvidia,aspm-pwr-on-t-us:
171    description: Power On time for proper operation of ASPM to be specified in
172      microseconds
173
174  nvidia,aspm-l0s-entrance-latency-us:
175    description: ASPM L0s entrance latency to be specified in microseconds
176
177  vddio-pex-ctl-supply:
178    description: A phandle to the regulator supply for PCIe side band signals.
179
180  vpcie3v3-supply:
181    description: A phandle to the regulator node that supplies 3.3V to the slot
182      if the platform has one such slot, e.g., x16 slot owned by C5 controller
183      in p2972-0000 platform.
184
185  vpcie12v-supply:
186    description: A phandle to the regulator node that supplies 12V to the slot
187      if the platform has one such slot, e.g., x16 slot owned by C5 controller
188      in p2972-0000 platform.
189
190  nvidia,enable-srns:
191    description: |
192      This boolean property needs to be present if the controller is
193      configured to operate in SRNS (Separate Reference Clocks with No
194      Spread-Spectrum Clocking).  NOTE: This is applicable only for
195      Tegra234.
196
197    $ref: /schemas/types.yaml#/definitions/flag
198
199  nvidia,enable-ext-refclk:
200    description: |
201      This boolean property needs to be present if the controller is
202      configured to use the reference clocking coming in from an external
203      clock source instead of using the internal clock source.
204
205    $ref: /schemas/types.yaml#/definitions/flag
206
207allOf:
208  - $ref: /schemas/pci/snps,dw-pcie.yaml#
209  - if:
210      properties:
211        compatible:
212          contains:
213            enum:
214              - nvidia,tegra194-pcie
215    then:
216      properties:
217        reg:
218          maxItems: 4
219        reg-names:
220          maxItems: 4
221
222  - if:
223      properties:
224        compatible:
225          contains:
226            enum:
227              - nvidia,tegra234-pcie
228    then:
229      properties:
230        reg:
231          minItems: 5
232        reg-names:
233          minItems: 5
234
235unevaluatedProperties: false
236
237required:
238  - interrupts
239  - interrupt-names
240  - interrupt-map
241  - interrupt-map-mask
242  - clocks
243  - clock-names
244  - resets
245  - reset-names
246  - power-domains
247  - vddio-pex-ctl-supply
248  - num-lanes
249  - phys
250  - phy-names
251  - nvidia,bpmp
252
253examples:
254  - |
255    #include <dt-bindings/clock/tegra194-clock.h>
256    #include <dt-bindings/interrupt-controller/arm-gic.h>
257    #include <dt-bindings/power/tegra194-powergate.h>
258    #include <dt-bindings/reset/tegra194-reset.h>
259
260    bus@0 {
261        #address-cells = <2>;
262        #size-cells = <2>;
263        ranges = <0x0 0x0 0x0 0x8 0x0>;
264
265        pcie@14180000 {
266            compatible = "nvidia,tegra194-pcie";
267            power-domains = <&bpmp TEGRA194_POWER_DOMAIN_PCIEX8B>;
268            reg = <0x0 0x14180000 0x0 0x00020000>, /* appl registers (128K)      */
269                  <0x0 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
270                  <0x0 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
271                  <0x0 0x38080000 0x0 0x00040000>; /* DBI reg space (256K)       */
272            reg-names = "appl", "config", "atu_dma", "dbi";
273
274            #address-cells = <3>;
275            #size-cells = <2>;
276            device_type = "pci";
277            num-lanes = <8>;
278            linux,pci-domain = <0>;
279
280            pinctrl-names = "default";
281            pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
282
283            clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
284            clock-names = "core";
285
286            resets = <&bpmp TEGRA194_RESET_PEX0_CORE_0_APB>,
287                     <&bpmp TEGRA194_RESET_PEX0_CORE_0>;
288            reset-names = "apb", "core";
289
290            interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
291                         <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
292            interrupt-names = "intr", "msi";
293
294            #interrupt-cells = <1>;
295            interrupt-map-mask = <0 0 0 0>;
296            interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
297
298            nvidia,bpmp = <&bpmp 0>;
299
300            supports-clkreq;
301            nvidia,aspm-cmrt-us = <60>;
302            nvidia,aspm-pwr-on-t-us = <20>;
303            nvidia,aspm-l0s-entrance-latency-us = <3>;
304
305            bus-range = <0x0 0xff>;
306            ranges = <0x81000000 0x0  0x38100000 0x0  0x38100000 0x0 0x00100000>, /* downstream I/O */
307                     <0x82000000 0x0  0x38200000 0x0  0x38200000 0x0 0x01e00000>, /* non-prefetch memory */
308                     <0xc2000000 0x18 0x00000000 0x18 0x00000000 0x4 0x00000000>; /* prefetchable memory */
309
310            vddio-pex-ctl-supply = <&vdd_1v8ao>;
311            vpcie3v3-supply = <&vdd_3v3_pcie>;
312            vpcie12v-supply = <&vdd_12v_pcie>;
313
314            phys = <&p2u_hsio_2>, <&p2u_hsio_3>, <&p2u_hsio_4>,
315                   <&p2u_hsio_5>;
316            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
317        };
318    };
319
320  - |
321    #include <dt-bindings/clock/tegra234-clock.h>
322    #include <dt-bindings/interrupt-controller/arm-gic.h>
323    #include <dt-bindings/power/tegra234-powergate.h>
324    #include <dt-bindings/reset/tegra234-reset.h>
325
326    bus@0 {
327        #address-cells = <2>;
328        #size-cells = <2>;
329        ranges = <0x0 0x0 0x0 0x8 0x0>;
330
331        pcie@14160000 {
332            compatible = "nvidia,tegra234-pcie";
333            power-domains = <&bpmp TEGRA234_POWER_DOMAIN_PCIEX4BB>;
334            reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K)      */
335                  <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
336                  <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K)  */
337                  <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K)       */
338                  <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB)               */
339            reg-names = "appl", "config", "atu_dma", "dbi", "ecam";
340
341            #address-cells = <3>;
342            #size-cells = <2>;
343            device_type = "pci";
344            num-lanes = <4>;
345            num-viewport = <8>;
346            linux,pci-domain = <4>;
347
348            clocks = <&bpmp TEGRA234_CLK_PEX0_C4_CORE>;
349            clock-names = "core";
350
351            resets = <&bpmp TEGRA234_RESET_PEX0_CORE_4_APB>,
352                     <&bpmp TEGRA234_RESET_PEX0_CORE_4>;
353            reset-names = "apb", "core";
354
355            interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
356                         <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
357            interrupt-names = "intr", "msi";
358
359            #interrupt-cells = <1>;
360            interrupt-map-mask = <0 0 0 0>;
361            interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
362
363            nvidia,bpmp = <&bpmp 4>;
364
365            nvidia,aspm-cmrt-us = <60>;
366            nvidia,aspm-pwr-on-t-us = <20>;
367            nvidia,aspm-l0s-entrance-latency-us = <3>;
368
369            bus-range = <0x0 0xff>;
370            ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable */
371                     <0x02000000 0x0  0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable */
372                     <0x01000000 0x0  0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O */
373
374            vddio-pex-ctl-supply = <&p3701_vdd_AO_1v8>;
375
376            phys = <&p2u_hsio_4>, <&p2u_hsio_5>, <&p2u_hsio_6>,
377                   <&p2u_hsio_7>;
378            phy-names = "p2u-0", "p2u-1", "p2u-2", "p2u-3";
379        };
380    };
381