1* Marvell Armada 7K/8K PCIe interface
2
3This PCIe host controller is based on the Synopsys DesignWare PCIe IP
4and thus inherits all the common properties defined in snps,dw-pcie.yaml.
5
6Required properties:
7- compatible: "marvell,armada8k-pcie"
8- reg: must contain two register regions
9   - the control register region
10   - the config space region
11- reg-names:
12   - "ctrl" for the control register region
13   - "config" for the config space region
14- interrupts: Interrupt specifier for the PCIe controller
15- clocks: reference to the PCIe controller clocks
16- clock-names: mandatory if there is a second clock, in this case the
17   name must be "core" for the first clock and "reg" for the second
18   one
19
20Optional properties:
21- phys: phandle(s) to PHY node(s) following the generic PHY bindings.
22	Either 1, 2 or 4 PHYs might be needed depending on the number of
23	PCIe lanes.
24- phy-names: names of the PHYs corresponding to the number of lanes.
25	Must be "cp0-pcie0-x4-lane0-phy", "cp0-pcie0-x4-lane1-phy" for
26	2 PHYs.
27
28Example:
29
30	pcie@f2600000 {
31		compatible = "marvell,armada8k-pcie", "snps,dw-pcie";
32		reg = <0 0xf2600000 0 0x10000>, <0 0xf6f00000 0 0x80000>;
33		reg-names = "ctrl", "config";
34		#address-cells = <3>;
35		#size-cells = <2>;
36		#interrupt-cells = <1>;
37		device_type = "pci";
38		dma-coherent;
39
40		bus-range = <0 0xff>;
41		ranges = <0x81000000 0 0xf9000000 0  0xf9000000 0 0x10000	/* downstream I/O */
42			  0x82000000 0 0xf6000000 0  0xf6000000 0 0xf00000>;	/* non-prefetchable memory */
43		interrupt-map-mask = <0 0 0 0>;
44		interrupt-map = <0 0 0 0 &gic 0 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
45		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
46		num-lanes = <1>;
47		clocks = <&cpm_syscon0 1 13>;
48	};
49