1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Samsung SoC series UFS PHY Device Tree Bindings
8
9maintainers:
10  - Alim Akhtar <alim.akhtar@samsung.com>
11
12properties:
13  "#phy-cells":
14    const: 0
15
16  compatible:
17    enum:
18      - samsung,exynos7-ufs-phy
19
20  reg:
21    maxItems: 1
22
23  reg-names:
24    items:
25      - const: phy-pma
26
27  clocks:
28    items:
29      - description: PLL reference clock
30      - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
31      - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
32      - description: symbol clock for output symbol ( tx0 symbol clock)
33
34  clock-names:
35    items:
36      - const: ref_clk
37      - const: rx1_symbol_clk
38      - const: rx0_symbol_clk
39      - const: tx0_symbol_clk
40
41  samsung,pmu-syscon:
42    $ref: '/schemas/types.yaml#/definitions/phandle'
43    description: phandle for PMU system controller interface, used to
44                 control pmu registers bits for ufs m-phy
45
46required:
47  - "#phy-cells"
48  - compatible
49  - reg
50  - reg-names
51  - clocks
52  - clock-names
53  - samsung,pmu-syscon
54
55additionalProperties: false
56
57examples:
58  - |
59    #include <dt-bindings/clock/exynos7-clk.h>
60
61    ufs_phy: ufs-phy@15571800 {
62        compatible = "samsung,exynos7-ufs-phy";
63        reg = <0x15571800 0x240>;
64        reg-names = "phy-pma";
65        samsung,pmu-syscon = <&pmu_system_controller>;
66        #phy-cells = <0>;
67        clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
68                 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
69                 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
70                 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
71        clock-names = "ref_clk", "rx1_symbol_clk",
72                      "rx0_symbol_clk", "tx0_symbol_clk";
73
74    };
75...
76