1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
3%YAML 1.2
4---
5$id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
6$schema: "http://devicetree.org/meta-schemas/core.yaml#"
7
8title: TI J721E WIZ (SERDES Wrapper)
9
10maintainers:
11  - Kishon Vijay Abraham I <kishon@ti.com>
12
13properties:
14  compatible:
15    enum:
16      - ti,j721e-wiz-16g
17      - ti,j721e-wiz-10g
18      - ti,am64-wiz-10g
19
20  power-domains:
21    maxItems: 1
22
23  clocks:
24    maxItems: 3
25    description: clock-specifier to represent input to the WIZ
26
27  clock-names:
28    items:
29      - const: fck
30      - const: core_ref_clk
31      - const: ext_ref_clk
32
33  num-lanes:
34    minimum: 1
35    maximum: 4
36
37  "#address-cells":
38    const: 1
39
40  "#size-cells":
41    const: 1
42
43  "#reset-cells":
44    const: 1
45
46  "#clock-cells":
47    const: 1
48
49  ranges: true
50
51  assigned-clocks:
52    minItems: 1
53    maxItems: 2
54
55  assigned-clock-parents:
56    minItems: 1
57    maxItems: 2
58
59  assigned-clock-rates:
60    minItems: 1
61    maxItems: 2
62
63  typec-dir-gpios:
64    maxItems: 1
65    description:
66      GPIO to signal Type-C cable orientation for lane swap.
67      If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
68      achieve the funtionality of an external type-C plug flip mux.
69
70  typec-dir-debounce-ms:
71    minimum: 100
72    maximum: 1000
73    default: 100
74    description:
75      Number of milliseconds to wait before sampling typec-dir-gpio.
76      If not specified, the default debounce of 100ms will be used.
77      Type-C spec states minimum CC pin debounce of 100 ms and maximum
78      of 200 ms. However, some solutions might need more than 200 ms.
79
80  refclk-dig:
81    type: object
82    description: |
83      WIZ node should have subnode for refclk_dig to select the reference
84      clock source for the reference clock used in the PHY and PMA digital
85      logic.
86    properties:
87      clocks:
88        minItems: 2
89        maxItems: 4
90        description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
91          the inputs to refclk_dig
92
93      "#clock-cells":
94        const: 0
95
96      assigned-clocks:
97        maxItems: 1
98
99      assigned-clock-parents:
100        maxItems: 1
101
102    required:
103      - clocks
104      - "#clock-cells"
105      - assigned-clocks
106      - assigned-clock-parents
107
108patternProperties:
109  "^pll[0|1]-refclk$":
110    type: object
111    description: |
112      WIZ node should have subnodes for each of the PLLs present in
113      the SERDES.
114    properties:
115      clocks:
116        maxItems: 2
117        description: Phandle to clock nodes representing the two inputs to PLL.
118
119      "#clock-cells":
120        const: 0
121
122      assigned-clocks:
123        maxItems: 1
124
125      assigned-clock-parents:
126        maxItems: 1
127
128    required:
129      - clocks
130      - "#clock-cells"
131      - assigned-clocks
132      - assigned-clock-parents
133
134  "^cmn-refclk1?-dig-div$":
135    type: object
136    description:
137      WIZ node should have subnodes for each of the PMA common refclock
138      provided by the SERDES.
139    properties:
140      clocks:
141        maxItems: 1
142        description: Phandle to the clock node representing the input to the
143          divider clock.
144
145      "#clock-cells":
146        const: 0
147
148    required:
149      - clocks
150      - "#clock-cells"
151
152  "^serdes@[0-9a-f]+$":
153    type: object
154    description: |
155      WIZ node should have '1' subnode for the SERDES. It could be either
156      Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
157      bindings specified in
158      Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
159      Torrent SERDES should follow the bindings specified in
160      Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
161
162required:
163  - compatible
164  - power-domains
165  - clocks
166  - clock-names
167  - num-lanes
168  - "#address-cells"
169  - "#size-cells"
170  - "#reset-cells"
171  - ranges
172
173additionalProperties: false
174
175examples:
176  - |
177    #include <dt-bindings/soc/ti,sci_pm_domain.h>
178
179    wiz@5000000 {
180           compatible = "ti,j721e-wiz-16g";
181           #address-cells = <1>;
182           #size-cells = <1>;
183           power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
184           clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
185           clock-names = "fck", "core_ref_clk", "ext_ref_clk";
186           assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
187           assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
188           num-lanes = <2>;
189           #reset-cells = <1>;
190           ranges = <0x5000000 0x5000000 0x10000>;
191
192           pll0-refclk {
193                  clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
194                  #clock-cells = <0>;
195                  assigned-clocks = <&wiz1_pll0_refclk>;
196                  assigned-clock-parents = <&k3_clks 293 13>;
197           };
198
199           pll1-refclk {
200                  clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
201                  #clock-cells = <0>;
202                  assigned-clocks = <&wiz1_pll1_refclk>;
203                  assigned-clock-parents = <&k3_clks 293 0>;
204           };
205
206           cmn-refclk-dig-div {
207                  clocks = <&wiz1_refclk_dig>;
208                  #clock-cells = <0>;
209           };
210
211           cmn-refclk1-dig-div {
212                  clocks = <&wiz1_pll1_refclk>;
213                  #clock-cells = <0>;
214           };
215
216           refclk-dig {
217                  clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
218                          <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
219                  #clock-cells = <0>;
220                  assigned-clocks = <&wiz0_refclk_dig>;
221                  assigned-clock-parents = <&k3_clks 292 11>;
222           };
223
224           serdes@5000000 {
225                  compatible = "ti,sierra-phy-t0";
226                  reg-names = "serdes";
227                  reg = <0x5000000 0x10000>;
228                  #address-cells = <1>;
229                  #size-cells = <0>;
230                  resets = <&serdes_wiz0 0>;
231                  reset-names = "sierra_reset";
232                  clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
233                  clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
234           };
235    };
236