1Actions Semi S700 Pin Controller
2
3This binding describes the pin controller found in the S700 SoC.
4
5Required Properties:
6
7- compatible:   Should be "actions,s700-pinctrl"
8- reg:          Should contain the register base address and size of
9		the pin controller.
10- clocks:       phandle of the clock feeding the pin controller
11- gpio-controller: Marks the device node as a GPIO controller.
12- gpio-ranges: Specifies the mapping between gpio controller and
13               pin-controller pins.
14- #gpio-cells: Should be two. The first cell is the gpio pin number
15		and the second cell is used for optional parameters.
16- interrupt-controller: Marks the device node as an interrupt controller.
17- #interrupt-cells: Specifies the number of cells needed to encode an
18		interrupt.  Shall be set to 2.  The first cell
19		defines the interrupt number, the second encodes
20		the trigger flags described in
21		bindings/interrupt-controller/interrupts.txt
22- interrupts: The interrupt outputs from the controller. There is one GPIO
23              interrupt per GPIO bank. The number of interrupts listed depends
24              on the number of GPIO banks on the SoC. The interrupts must be
25              ordered by bank, starting with bank 0.
26
27Please refer to pinctrl-bindings.txt in this directory for details of the
28common pinctrl bindings used by client devices, including the meaning of the
29phrase "pin configuration node".
30
31The pin configuration nodes act as a container for an arbitrary number of
32subnodes. Each of these subnodes represents some desired configuration for a
33pin, a group, or a list of pins or groups. This configuration can include the
34mux function to select on those group(s), and various pin configuration
35parameters, such as pull-up, drive strength, etc.
36
37PIN CONFIGURATION NODES:
38
39The name of each subnode is not important; all subnodes should be enumerated
40and processed purely based on their content.
41
42Each subnode only affects those parameters that are explicitly listed. In
43other words, a subnode that lists a mux function but no pin configuration
44parameters implies no information about any pin configuration parameters.
45Similarly, a pin subnode that describes a pullup parameter implies no
46information about e.g. the mux function.
47
48Pinmux functions are available only for the pin groups while pinconf
49parameters are available for both pin groups and individual pins.
50
51The following generic properties as defined in pinctrl-bindings.txt are valid
52to specify in a pin configuration subnode:
53
54Required Properties:
55
56- pins:		An array of strings, each string containing the name of a pin.
57		These pins are used for selecting the pull control and schmitt
58		trigger parameters. The following are the list of pins
59		available:
60
61		eth_txd0, eth_txd1, eth_txd2, eth_txd3, eth_txen, eth_rxer,
62		eth_crs_dv, eth_rxd1, eth_rxd0, eth_rxd2, eth_rxd3, eth_ref_clk,
63		eth_mdc, eth_mdio, sirq0, sirq1, sirq2, i2s_d0, i2s_bclk0,
64		i2s_lrclk0, i2s_mclk0, i2s_d1, i2s_bclk1, i2s_lrclk1, i2s_mclk1,
65		pcm1_in, pcm1_clk, pcm1_sync, pcm1_out, ks_in0, ks_in1, ks_in2,
66		ks_in3, ks_out0, ks_out1, ks_out2, lvds_oep, lvds_oen, lvds_odp,
67		lvds_odn, lvds_ocp, lvds_ocn, lvds_obp, lvds_obn, lvds_oap,
68		lvds_oan, lvds_eep, lvds_een, lvds_edp, lvds_edn, lvds_ecp,
69		lvds_ecn, lvds_ebp, lvds_ebn, lvds_eap, lvds_ean, lcd0_d18,
70		lcd0_d2, dsi_dp3, dsi_dn3, dsi_dp1, dsi_dn1, dsi_cp, dsi_cn,
71		dsi_dp0, dsi_dn0, dsi_dp2, dsi_dn2, sd0_d0, sd0_d1, sd0_d2,
72		sd0_d3, sd1_d0, sd1_d1, sd1_d2, sd1_d3, sd0_cmd, sd0_clk,
73		sd1_cmd, sd1_clk, spi0_ss, spi0_miso, uart0_rx, uart0_tx,
74		uart2_rx, uart2_tx, uart2_rtsb, uart2_ctsb, uart3_rx, uart3_tx,
75		uart3_rtsb, uart3_ctsb, i2c0_sclk, i2c0_sdata, i2c1_sclk,
76		i2c1_sdata, i2c2_sdata, csi_dn0, csi_dp0, csi_dn1, csi_dp1,
77		csi_cn, csi_cp, csi_dn2, csi_dp2, csi_dn3, csi_dp3,
78		sensor0_pclk, sensor0_ckout, dnand_d0, dnand_d1, dnand_d2,
79		dnand_d3, dnand_d4, dnand_d5, dnand_d6, dnand_d7, dnand_wrb,
80		dnand_rdb, dnand_rdbn, dnand_dqs, dnand_dqsn, dnand_rb0,
81		dnand_ale, dnand_cle, dnand_ceb0, dnand_ceb1, dnand_ceb2,
82		dnand_ceb3, porb, clko_25m, bsel, pkg0, pkg1, pkg2, pkg3
83
84- groups:       An array of strings, each string containing the name of a pin
85                group. These pin groups are used for selecting the pinmux
86                functions.
87		rgmii_txd23_mfp, rgmii_rxd2_mfp, rgmii_rxd3_mfp, lcd0_d18_mfp,
88		rgmii_txd01_mfp, rgmii_txd0_mfp, rgmii_txd1_mfp, rgmii_txen_mfp,
89		rgmii_rxen_mfp, rgmii_rxd1_mfp, rgmii_rxd0_mfp, rgmii_ref_clk_mfp,
90		i2s_d0_mfp, i2s_pcm1_mfp, i2s0_pcm0_mfp, i2s1_pcm0_mfp,
91		i2s_d1_mfp, ks_in2_mfp, ks_in1_mfp, ks_in0_mfp, ks_in3_mfp,
92		ks_out0_mfp, ks_out1_mfp, ks_out2_mfp, lvds_o_pn_mfp, dsi_dn0_mfp,
93		dsi_dp2_mfp, lcd0_d2_mfp, dsi_dp3_mfp, dsi_dn3_mfp, dsi_dp0_mfp,
94		lvds_ee_pn_mfp, uart2_rx_tx_mfp, spi0_i2c_pcm_mfp, dsi_dnp1_cp_d2_mfp,
95		dsi_dnp1_cp_d17_mfp, lvds_e_pn_mfp, dsi_dn2_mfp, uart2_rtsb_mfp,
96		uart2_ctsb_mfp, uart3_rtsb_mfp, uart3_ctsb_mfp, sd0_d0_mfp, sd0_d1_mfp,
97		sd0_d2_d3_mfp, sd1_d0_d3_mfp, sd0_cmd_mfp, sd0_clk_mfp, sd1_cmd_mfp,
98		uart0_rx_mfp, clko_25m_mfp, csi_cn_cp_mfp, sens0_ckout_mfp, uart0_tx_mfp,
99		i2c0_mfp, csi_dn_dp_mfp, sen0_pclk_mfp, pcm1_in_mfp, pcm1_clk_mfp,
100		pcm1_sync_mfp, pcm1_out_mfp, dnand_data_wr_mfp, dnand_acle_ce0_mfp,
101		nand_ceb2_mfp, nand_ceb3_mfp
102
103		These pin groups are used for selecting the drive strength
104		parameters.
105
106		sirq_drv, rgmii_txd23_drv, rgmii_rxd23_drv, rgmii_txd01_txen_drv,
107		rgmii_rxer_drv, rgmii_crs_drv, rgmii_rxd10_drv, rgmii_ref_clk_drv,
108		smi_mdc_mdio_drv, i2s_d0_drv, i2s_bclk0_drv, i2s3_drv, i2s13_drv,
109		pcm1_drv, ks_in_drv, ks_out_drv, lvds_all_drv, lcd_d18_d2_drv,
110		dsi_all_drv, sd0_d0_d3_drv, sd0_cmd_drv, sd0_clk_drv, spi0_all_drv,
111		uart0_rx_drv, uart0_tx_drv, uart2_all_drv, i2c0_all_drv, i2c12_all_drv,
112		sens0_pclk_drv, sens0_ckout_drv, uart3_all_drv
113
114- function:	An array of strings, each string containing the name of the
115		pinmux functions. These functions can only be selected by
116		the corresponding pin groups. The following are the list of
117		pinmux functions available:
118
119		nor, eth_rgmii, eth_sgmii, spi0, spi1, spi2, spi3, seNs0, sens1,
120		uart0, uart1, uart2, uart3, uart4, uart5, uart6, i2s0, i2s1,
121		pcm1, pcm0, ks, jtag, pwm0, pwm1, pwm2, pwm3, pwm4, pwm5, p0,
122		sd0, sd1, sd2, i2c0, i2c1, i2c2, i2c3, dsi, lvds, usb30,
123		clko_25m, mipi_csi, nand, spdif, sirq0, sirq1, sirq2, bt, lcd0
124
125Optional Properties:
126
127- bias-pull-down: No arguments. The specified pins should be configured as
128		pull down.
129- bias-pull-up:   No arguments. The specified pins should be configured as
130		pull up.
131- input-schmitt-enable: No arguments: Enable schmitt trigger for the specified
132		pins
133- input-schmitt-disable: No arguments: Disable schmitt trigger for the specified
134		pins
135- drive-strength: Integer. Selects the drive strength for the specified
136		pins in mA.
137		Valid values are:
138		<2>
139		<4>
140		<8>
141		<12>
142
143Example:
144
145	pinctrl: pinctrl@e01b0000 {
146		compatible = "actions,s700-pinctrl";
147		reg = <0x0 0xe01b0000 0x0 0x1000>;
148		clocks = <&cmu CLK_GPIO>;
149		gpio-controller;
150		gpio-ranges = <&pinctrl 0 0 136>;
151		#gpio-cells = <2>;
152		interrupt-controller;
153		#interrupt-cells = <2>;
154                interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
155                             <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
156                             <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
157                             <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
158                             <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
159
160		uart3-default: uart3-default {
161			pinmux {
162				groups = "uart3_rtsb_mfp", "uart3_ctsb_mfp";
163				function = "uart3";
164			};
165			pinconf {
166				groups = "uart3_all_drv";
167				drive-strength = <2>;
168			};
169		};
170	};
171