1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/mediatek,pinctrl-mt6795.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mediatek MT6795 Pin Controller
8
9maintainers:
10  - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
11  - Sean Wang <sean.wang@kernel.org>
12
13description: |
14  The Mediatek's Pin controller is used to control SoC pins.
15
16properties:
17  compatible:
18    const: mediatek,mt6795-pinctrl
19
20  gpio-controller: true
21
22  '#gpio-cells':
23    description: |
24      Number of cells in GPIO specifier. Since the generic GPIO binding is used,
25      the amount of cells must be specified as 2. See the below
26      mentioned gpio binding representation for description of particular cells.
27    const: 2
28
29  gpio-ranges:
30    description: GPIO valid number range.
31    maxItems: 1
32
33  reg:
34    description:
35      Physical address base for gpio base and eint registers.
36    minItems: 2
37
38  reg-names:
39    items:
40      - const: base
41      - const: eint
42
43  interrupt-controller: true
44
45  '#interrupt-cells':
46    const: 2
47
48  interrupts:
49    description: Interrupt outputs to the system interrupt controller (sysirq).
50    minItems: 1
51    items:
52      - description: EINT interrupt
53      - description: EINT event_b interrupt
54
55# PIN CONFIGURATION NODES
56patternProperties:
57  '-pins$':
58    type: object
59    additionalProperties: false
60    patternProperties:
61      '^pins':
62        type: object
63        additionalProperties: false
64        description: |
65          A pinctrl node should contain at least one subnodes representing the
66          pinctrl groups available on the machine. Each subnode will list the
67          pins it needs, and how they should be configured, with regard to muxer
68          configuration, pullups, drive strength, input enable/disable and
69          input schmitt.
70          An example of using macro:
71          pincontroller {
72            /* GPIO0 set as multifunction GPIO0 */
73            gpio-pins {
74              pins {
75                pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
76              }
77            };
78            /* GPIO45 set as multifunction SDA0 */
79            i2c0-pins {
80              pins {
81                pinmux = <PINMUX_GPIO45__FUNC_SDA0>;
82              }
83            };
84          };
85        $ref: "pinmux-node.yaml"
86
87        properties:
88          pinmux:
89            description: |
90              Integer array, represents gpio pin number and mux setting.
91              Supported pin number and mux varies for different SoCs, and are
92              defined as macros in dt-bindings/pinctrl/<soc>-pinfunc.h
93              directly.
94
95          drive-strength:
96            enum: [2, 4, 6, 8, 10, 12, 14, 16]
97
98          bias-pull-down:
99            oneOf:
100              - type: boolean
101              - enum: [100, 101, 102, 103]
102                description: mt6795 pull down PUPD/R0/R1 type define value.
103            description: |
104               For normal pull down type, it is not necessary to specify R1R0
105               values; When pull down type is PUPD/R0/R1, adding R1R0 defines
106               will set different resistance values.
107
108          bias-pull-up:
109            oneOf:
110              - type: boolean
111              - enum: [100, 101, 102, 103]
112                description: mt6795 pull up PUPD/R0/R1 type define value.
113            description: |
114               For normal pull up type, it is not necessary to specify R1R0
115               values; When pull up type is PUPD/R0/R1, adding R1R0 defines
116               will set different resistance values.
117
118          bias-disable: true
119
120          output-high: true
121
122          output-low: true
123
124          input-enable: true
125
126          input-disable: true
127
128          input-schmitt-enable: true
129
130          input-schmitt-disable: true
131
132          mediatek,pull-up-adv:
133            description: |
134              Pull up setings for 2 pull resistors, R0 and R1. User can
135              configure those special pins. Valid arguments are described as below:
136              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
137              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
138              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
139              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
140            $ref: /schemas/types.yaml#/definitions/uint32
141            enum: [0, 1, 2, 3]
142
143          mediatek,pull-down-adv:
144            description: |
145              Pull down settings for 2 pull resistors, R0 and R1. User can
146              configure those special pins. Valid arguments are described as below:
147              0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
148              1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
149              2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
150              3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
151            $ref: /schemas/types.yaml#/definitions/uint32
152            enum: [0, 1, 2, 3]
153
154        required:
155          - pinmux
156
157allOf:
158  - $ref: "pinctrl.yaml#"
159
160required:
161  - compatible
162  - reg
163  - reg-names
164  - interrupts
165  - interrupt-controller
166  - '#interrupt-cells'
167  - gpio-controller
168  - '#gpio-cells'
169  - gpio-ranges
170
171additionalProperties: false
172
173examples:
174  - |
175    #include <dt-bindings/interrupt-controller/arm-gic.h>
176    #include <dt-bindings/interrupt-controller/irq.h>
177    #include <dt-bindings/pinctrl/mt6795-pinfunc.h>
178
179    soc {
180        #address-cells = <2>;
181        #size-cells = <2>;
182
183        pio: pinctrl@10005000 {
184            compatible = "mediatek,mt6795-pinctrl";
185            reg = <0 0x10005000 0 0x1000>, <0 0x1000b000 0 0x1000>;
186            reg-names = "base", "eint";
187            gpio-controller;
188            #gpio-cells = <2>;
189            gpio-ranges = <&pio 0 0 196>;
190            interrupt-controller;
191            interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
192            #interrupt-cells = <2>;
193
194            i2c0-pins {
195                pins-sda-scl {
196                    pinmux = <PINMUX_GPIO45__FUNC_SDA0>,
197                             <PINMUX_GPIO46__FUNC_SCL0>;
198                };
199            };
200
201            mmc0-pins {
202                pins-cmd-dat {
203                    pinmux = <PINMUX_GPIO154__FUNC_MSDC0_DAT0>,
204                             <PINMUX_GPIO155__FUNC_MSDC0_DAT1>,
205                             <PINMUX_GPIO156__FUNC_MSDC0_DAT2>,
206                             <PINMUX_GPIO157__FUNC_MSDC0_DAT3>,
207                             <PINMUX_GPIO158__FUNC_MSDC0_DAT4>,
208                             <PINMUX_GPIO159__FUNC_MSDC0_DAT5>,
209                             <PINMUX_GPIO160__FUNC_MSDC0_DAT6>,
210                             <PINMUX_GPIO161__FUNC_MSDC0_DAT7>,
211                             <PINMUX_GPIO162__FUNC_MSDC0_CMD>;
212                    input-enable;
213                    bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
214                };
215
216                pins-clk {
217                    pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>;
218                    bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
219                };
220
221                pins-rst {
222                    pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>;
223                    bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
224                };
225            };
226        };
227    };
228