1NVIDIA Tegra20 pinmux controller
2
3Required properties:
4- compatible: "nvidia,tegra20-pinmux"
5- reg: Should contain the register physical address and length for each of
6  the tri-state, mux, pull-up/down, and pad control register sets.
7
8Please refer to pinctrl-bindings.txt in this directory for details of the
9common pinctrl bindings used by client devices, including the meaning of the
10phrase "pin configuration node".
11
12Tegra's pin configuration nodes act as a container for an arbitrary number of
13subnodes. Each of these subnodes represents some desired configuration for a
14pin, a group, or a list of pins or groups. This configuration can include the
15mux function to select on those pin(s)/group(s), and various pin configuration
16parameters, such as pull-up, tristate, drive strength, etc.
17
18The name of each subnode is not important; all subnodes should be enumerated
19and processed purely based on their content.
20
21Each subnode only affects those parameters that are explicitly listed. In
22other words, a subnode that lists a mux function but no pin configuration
23parameters implies no information about any pin configuration parameters.
24Similarly, a pin subnode that describes a pullup parameter implies no
25information about e.g. the mux function or tristate parameter. For this
26reason, even seemingly boolean values are actually tristates in this binding:
27unspecified, off, or on. Unspecified is represented as an absent property,
28and off/on are represented as integer values 0 and 1.
29
30Required subnode-properties:
31- nvidia,pins : An array of strings. Each string contains the name of a pin or
32    group. Valid values for these names are listed below.
33
34Optional subnode-properties:
35- nvidia,function: A string containing the name of the function to mux to the
36  pin or group. Valid values for function names are listed below. See the Tegra
37  TRM to determine which are valid for each pin or group.
38- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
39    0: none, 1: down, 2: up.
40- nvidia,tristate: Integer.
41    0: drive, 1: tristate.
42- nvidia,high-speed-mode: Integer. Enable high speed mode the pins.
43    0: no, 1: yes.
44- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
45    0: no, 1: yes.
46- nvidia,low-power-mode: Integer. Valid values 0-3. 0 is least power, 3 is
47    most power. Controls the drive power or current. See "Low Power Mode"
48    or "LPMD1" and "LPMD0" in the Tegra TRM.
49- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
50    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
51    Tegra TRM.
52- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
53    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
54    Tegra TRM.
55- nvidia,slew-rate-rising: Integer. Controls rising signal slew rate. 0 is
56    fastest. The range of valid values depends on the pingroup. See
57    "DRVDN_SLWR" in the Tegra TRM.
58- nvidia,slew-rate-falling: Integer. Controls falling signal slew rate. 0 is
59    fastest. The range of valid values depends on the pingroup. See
60    "DRVUP_SLWF" in the Tegra TRM.
61
62Note that many of these properties are only valid for certain specific pins
63or groups. See the Tegra TRM and various pinmux spreadsheets for complete
64details regarding which groups support which functionality. The Linux pinctrl
65driver may also be a useful reference, since it consolidates, disambiguates,
66and corrects data from all those sources.
67
68Valid values for pin and group names are:
69
70  mux groups:
71
72    These all support nvidia,function, nvidia,tristate, and many support
73    nvidia,pull.
74
75    ata, atb, atc, atd, ate, cdev1, cdev2, crtp, csus, dap1, dap2, dap3, dap4,
76    ddc, dta, dtb, dtc, dtd, dte, dtf, gma, gmb, gmc, gmd, gme, gpu, gpu7,
77    gpv, hdint, i2cp, irrx, irtx, kbca, kbcb, kbcc, kbcd, kbce, kbcf, lcsn,
78    ld0, ld1, ld2, ld3, ld4, ld5, ld6, ld7, ld8, ld9, ld10, ld11, ld12, ld13,
79    ld14, ld15, ld16, ld17, ldc, ldi, lhp0, lhp1, lhp2, lhs, lm0, lm1, lpp,
80    lpw0, lpw1, lpw2, lsc0, lsc1, lsck, lsda, lsdi, lspi, lvp0, lvp1, lvs,
81    owc, pmc, pta, rm, sdb, sdc, sdd, sdio1, slxa, slxc, slxd, slxk, spdi,
82    spdo, spia, spib, spic, spid, spie, spif, spig, spih, uaa, uab, uac, uad,
83    uca, ucb, uda.
84
85  tristate groups:
86
87    These only support nvidia,pull.
88
89    ck32, ddrc, pmca, pmcb, pmcc, pmcd, pmce, xm2c, xm2d, ls, lc, ld17_0,
90    ld19_18, ld21_20, ld23_22.
91
92  drive groups:
93
94    With some exceptions, these support nvidia,high-speed-mode,
95    nvidia,schmitt, nvidia,low-power-mode, nvidia,pull-down-strength,
96    nvidia,pull-up-strength, nvidia,slew-rate-rising, nvidia,slew-rate-falling.
97
98    drive_ao1, drive_ao2, drive_at1, drive_at2, drive_cdev1, drive_cdev2,
99    drive_csus, drive_dap1, drive_dap2, drive_dap3, drive_dap4, drive_dbg,
100    drive_lcd1, drive_lcd2, drive_sdmmc2, drive_sdmmc3, drive_spi, drive_uaa,
101    drive_uab, drive_uart2, drive_uart3, drive_vi1, drive_vi2, drive_xm2a,
102    drive_xm2c, drive_xm2d, drive_xm2clk, drive_sdio1, drive_crt, drive_ddc,
103    drive_gma, drive_gmb, drive_gmc, drive_gmd, drive_gme, drive_owr,
104    drive_uda.
105
106Valid values for nvidia,functions are:
107
108  ahb_clk, apb_clk, audio_sync, crt, dap1, dap2, dap3, dap4, dap5,
109  displaya, displayb, emc_test0_dll, emc_test1_dll, gmi, gmi_int,
110  hdmi, i2cp, i2c1, i2c2, i2c3, ide, irda, kbc, mio, mipi_hs, nand,
111  osc, owr, pcie, plla_out, pllc_out1, pllm_out1, pllp_out2, pllp_out3,
112  pllp_out4, pwm, pwr_intr, pwr_on, rsvd1, rsvd2, rsvd3, rsvd4, rtck,
113  sdio1, sdio2, sdio3, sdio4, sflash, spdif, spi1, spi2, spi2_alt,
114  spi3, spi4, trace, twc, uarta, uartb, uartc, uartd, uarte, ulpi,
115  vi, vi_sensor_clk, xio
116
117Example:
118
119	pinctrl@70000000 {
120		compatible = "nvidia,tegra20-pinmux";
121		reg = < 0x70000014 0x10    /* Tri-state registers */
122			0x70000080 0x20    /* Mux registers */
123			0x700000a0 0x14    /* Pull-up/down registers */
124			0x70000868 0xa8 >; /* Pad control registers */
125	};
126
127Example board file extract:
128
129	pinctrl@70000000 {
130		sdio4_default: sdio4_default {
131			atb {
132				nvidia,pins = "atb", "gma", "gme";
133				nvidia,function = "sdio4";
134				nvidia,pull = <0>;
135				nvidia,tristate = <0>;
136			};
137		};
138	};
139
140	sdhci@c8000600 {
141		pinctrl-names = "default";
142		pinctrl-0 = <&sdio4_default>;
143	};
144