1*ST pin controller.
2
3Each multi-function pin is controlled, driven and routed through the
4PIO multiplexing block. Each pin supports GPIO functionality (ALT0)
5and multiple alternate functions(ALT1 - ALTx) that directly connect
6the pin to different hardware blocks.
7
8When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
9Pull Up (PU) are driven by the related PIO block.
10
11ST pinctrl driver controls PIO multiplexing block and also interacts with
12gpio driver to configure a pin.
13
14GPIO bank can have one of the two possible types of interrupt-wirings.
15
16First type is via irqmux, single interrupt is used by multiple gpio banks. This
17reduces number of overall interrupts numbers required. All these banks belong to
18a single pincontroller.
19		  _________
20		 |	   |----> [gpio-bank (n)    ]
21		 |	   |----> [gpio-bank (n + 1)]
22	[irqN]-- | irq-mux |----> [gpio-bank (n + 2)]
23		 |	   |----> [gpio-bank (...  )]
24		 |_________|----> [gpio-bank (n + 7)]
25
26Second type has a dedicated interrupt per gpio bank.
27
28	[irqN]----> [gpio-bank (n)]
29
30
31Pin controller node:
32Required properties:
33- compatible	: should be "st,stih407-<pio-block>-pinctrl"
34- st,syscfg		: Should be a phandle of the syscfg node.
35- st,retime-pin-mask	: Should be mask to specify which pins can be retimed.
36	If the property is not present, it is assumed that all the pins in the
37	bank are capable of retiming. Retiming is mainly used to improve the
38	IO timing margins of external synchronous interfaces.
39- ranges : defines mapping between pin controller node (parent) to gpio-bank
40  node (children).
41
42Optional properties:
43- interrupts	: Interrupt number of the irqmux. If the interrupt is shared
44  with other gpio banks via irqmux.
45  a irqline and gpio banks.
46- reg		: irqmux memory resource. If irqmux is present.
47- reg-names	: irqmux resource should be named as "irqmux".
48
49GPIO controller/bank node.
50Required properties:
51- gpio-controller : Indicates this device is a GPIO controller
52- #gpio-cells	  : Must be two.
53     - First cell: specifies the pin number inside the controller
54     - Second cell: specifies whether the pin is logically inverted.
55       - 0 = active high
56       - 1 = active low
57- st,bank-name	  : Should be a name string for this bank as specified in
58  datasheet.
59
60Optional properties:
61- interrupts	: Interrupt number for this gpio bank. If there is a dedicated
62  interrupt wired up for this gpio bank.
63
64- interrupt-controller : Indicates this device is a interrupt controller. GPIO
65  bank can be an interrupt controller iff one of the interrupt type either via
66irqmux or a dedicated interrupt per bank is specified.
67
68- #interrupt-cells: the value of this property should be 2.
69     - First Cell: represents the external gpio interrupt number local to the
70       gpio interrupt space of the controller.
71     - Second Cell: flags to identify the type of the interrupt
72       - 1 = rising edge triggered
73       - 2 = falling edge triggered
74       - 3 = rising and falling edge triggered
75       - 4 = high level triggered
76       - 8 = low level triggered
77for related macros look in:
78include/dt-bindings/interrupt-controller/irq.h
79
80Example:
81	pin-controller-sbc {
82		#address-cells = <1>;
83		#size-cells = <1>;
84		compatible = "st,stih407-sbc-pinctrl";
85		st,syscfg = <&syscfg_sbc>;
86		reg = <0x0961f080 0x4>;
87		reg-names = "irqmux";
88		interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>;
89		interrupt-names = "irqmux";
90		ranges = <0 0x09610000 0x6000>;
91
92		pio0: gpio@9610000 {
93			gpio-controller;
94			#gpio-cells = <2>;
95			interrupt-controller;
96			#interrupt-cells = <2>;
97			reg = <0x0 0x100>;
98			st,bank-name = "PIO0";
99		};
100		...
101		pin-functions nodes follow...
102	};
103
104
105Contents of function subnode node:
106----------------------
107Required properties for pin configuration node:
108- st,pins	: Child node with list of pins with configuration.
109
110Below is the format of how each pin conf should look like.
111
112<bank offset mux mode rt_type rt_delay rt_clk>
113
114Every PIO is represented with 4-7 parameters depending on retime configuration.
115Each parameter is explained as below.
116
117-bank		: Should be bank phandle to which this PIO belongs.
118-offset		: Offset in the PIO bank.
119-mux		: Should be alternate function number associated this pin.
120		Use same numbers from datasheet.
121-mode		:pin configuration is selected from one of the below values.
122		IN
123		IN_PU
124		OUT
125		BIDIR
126		BIDIR_PU
127
128-rt_type	Retiming Configuration for the pin.
129		Possible retime configuration are:
130
131		-------		-------------
132		value		args
133		-------		-------------
134		NICLK		<delay> <clk>
135		ICLK_IO		<delay> <clk>
136		BYPASS		<delay>
137		DE_IO		<delay> <clk>
138		SE_ICLK_IO	<delay> <clk>
139		SE_NICLK_IO	<delay> <clk>
140
141- delay	is retime delay in pico seconds as mentioned in data sheet.
142
143- rt_clk	:clk to be use for retime.
144		Possible values are:
145		CLK_A
146		CLK_B
147		CLK_C
148		CLK_D
149
150Example of mmcclk pin which is a bi-direction pull pu with retime config
151as non inverted clock retimed with CLK_B and delay of 0 pico seconds:
152
153pin-controller {
154	...
155	mmc0 {
156		pinctrl_mmc: mmc {
157			st,pins {
158				mmcclk = <&PIO13 4 ALT4 BIDIR_PU NICLK 0 CLK_B>;
159				...
160			};
161		};
162	...
163	};
164};
165
166sdhci0:sdhci@fe810000{
167	...
168	interrupt-parent = <&pio3>;
169	#interrupt-cells = <2>;
170	interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; /* Interrupt line via PIO3-3 */
171	interrupt-names = "card-detect";
172	pinctrl-names = "default";
173	pinctrl-0	= <&pinctrl_mmc>;
174};
175