1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,qdu1000-tlmm.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. QDU1000/QRU1000 TLMM block
8
9maintainers:
10  - Melody Olvera <quic_molvera@quicinc.com>
11
12description: |
13  Top Level Mode Multiplexer pin controller found in the QDU1000 and
14  QRU1000 SoCs.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,qdu1000-tlmm
22
23  reg:
24    maxItems: 1
25
26  interrupts: true
27  interrupt-controller: true
28  "#interrupt-cells": true
29  gpio-controller: true
30
31  gpio-reserved-ranges:
32    minItems: 1
33    maxItems: 76
34
35  gpio-line-names:
36    maxItems: 151
37
38  "#gpio-cells": true
39  gpio-ranges: true
40  wakeup-parent: true
41
42patternProperties:
43  "-state$":
44    oneOf:
45      - $ref: "#/$defs/qcom-qdu1000-tlmm-state"
46      - patternProperties:
47          "-pins$":
48            $ref: "#/$defs/qcom-qdu1000-tlmm-state"
49        additionalProperties: false
50
51$defs:
52  qcom-qdu1000-tlmm-state:
53    type: object
54    description:
55      Pinctrl node's client devices use subnodes for desired pin configuration.
56      Client device subnodes use below standard properties.
57    $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
58    unevaluatedProperties: false
59
60    properties:
61      pins:
62        description:
63          List of gpio pins affected by the properties specified in this
64          subnode.
65        items:
66          oneOf:
67            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-4][0-9]|150)$"
68            - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data ]
69        minItems: 1
70        maxItems: 36
71
72      function:
73        description:
74          Specify the alternative function to be configured for the specified
75          pins.
76        enum: [ atest_char, atest_usb, char_exec, CMO_PRI, cmu_rng,
77                dbg_out_clk, ddr_bist, ddr_pxi1, ddr_pxi2, ddr_pxi3, ddr_pxi4,
78                ddr_pxi5, ddr_pxi6, ddr_pxi7, eth012_int_n, eth345_int_n,
79                gcc_gp1, gcc_gp2, gcc_gp3, gpio, gps_pps_in, hardsync_pps_in,
80                intr_c, jitter_bist_ref, pcie_clkreqn, phase_flag, pll_bist,
81                pll_clk, prng_rosc, qdss_cti, qdss_gpio, qlink0_enable,
82                qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
83                qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
84                qlink3_enable, qlink3_request, qlink3_wmss, qlink4_enable,
85                qlink4_request, qlink4_wmss, qlink5_enable, qlink5_request,
86                qlink5_wmss, qlink6_enable, qlink6_request, qlink6_wmss,
87                qlink7_enable, qlink7_request, qlink7_wmss, qspi_clk, qspi_cs,
88                qspi0, qspi1, qspi2, qspi3, qup00, qup01, qup02, qup03, qup04,
89                qup05, qup06, qup07, qup08, qup10, qup11, qup12, qup13, qup14,
90                qup15, qup16, qup17, qup20, qup21, qup22, SI5518_INT, smb_alert,
91                smb_clk, smb_dat, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2, tgu_ch3,
92                tgu_ch4, tgu_ch5, tgu_ch6, tgu_ch7, tmess_prng0, tmess_prng1,
93                tmess_prng2, tmess_prng3, tod_pps_in, tsense_pwm1, tsense_pwm2,
94                usb2phy_ac, usb_con_det, usb_dfp_en, usb_phy, vfr_0, vfr_1,
95                vsense_trigger ]
96
97    required:
98      - pins
99
100required:
101  - compatible
102  - reg
103
104additionalProperties: false
105
106examples:
107  - |
108    #include <dt-bindings/interrupt-controller/arm-gic.h>
109
110    pinctrl@f000000 {
111        compatible = "qcom,qdu1000-tlmm";
112        reg = <0xf000000 0x1000000>;
113        interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
114        gpio-controller;
115        #gpio-cells = <2>;
116        interrupt-controller;
117        #interrupt-cells = <2>;
118        gpio-ranges = <&tlmm 0 0 151>;
119        wakeup-parent = <&pdc>;
120
121        uart0-default-state {
122            pins = "gpio6", "gpio7", "gpio8", "gpio9";
123            function = "qup00";
124        };
125    };
126