1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SM8450 TLMM block
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description: |
13  This binding describes the Top Level Mode Multiplexer (TLMM) block found
14  in the SM8450 platform.
15
16allOf:
17  - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
18
19properties:
20  compatible:
21    const: qcom,sm8450-tlmm
22
23  reg:
24    maxItems: 1
25
26  interrupts: true
27  interrupt-controller: true
28  '#interrupt-cells': true
29  gpio-controller: true
30  gpio-reserved-ranges: true
31  '#gpio-cells': true
32  gpio-ranges: true
33  wakeup-parent: true
34
35required:
36  - compatible
37  - reg
38
39additionalProperties: false
40
41patternProperties:
42  '-state$':
43    oneOf:
44      - $ref: "#/$defs/qcom-sm8450-tlmm-state"
45      - patternProperties:
46          ".*":
47            $ref: "#/$defs/qcom-sm8450-tlmm-state"
48
49$defs:
50  qcom-sm8450-tlmm-state:
51    type: object
52    description:
53      Pinctrl node's client devices use subnodes for desired pin configuration.
54      Client device subnodes use below standard properties.
55    $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
56
57    properties:
58      pins:
59        description:
60          List of gpio pins affected by the properties specified in this
61          subnode.
62        items:
63          oneOf:
64            - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9])$"
65            - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
66        minItems: 1
67        maxItems: 36
68
69      function:
70        description:
71          Specify the alternative function to be configured for the specified
72          pins.
73        enum: [ aon_cam, atest_char, atest_usb, audio_ref, cam_mclk, cci_async,
74                cci_i2c, cci_timer, cmu_rng, coex_uart1, coex_uart2, cri_trng,
75                cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
76                ddr_pxi2, ddr_pxi3, dp_hot, gcc_gp1, gcc_gp2, gcc_gp3,
77                gpio, ibi_i3c, jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1,
78                mdp_vsync2, mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck,
79                mi2s0_ws, mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws,
80                mss_grfc0, mss_grfc1, mss_grfc10, mss_grfc11, mss_grfc12,
81                mss_grfc2, mss_grfc3, mss_grfc4, mss_grfc5, mss_grfc6,
82                mss_grfc7, mss_grfc8, mss_grfc9, nav, pcie0_clkreqn,
83                pcie1_clkreqn, phase_flag, pll_bist, pll_clk, pri_mi2s,
84                prng_rosc, qdss_cti, qdss_gpio, qlink0_enable, qlink0_request,
85                qlink0_wmss, qlink1_enable, qlink1_request, qlink1_wmss,
86                qlink2_enable, qlink2_request, qlink2_wmss, qspi0, qspi1,
87                qspi2, qspi3, qspi_clk, qspi_cs, qup0, qup1, qup10, qup11,
88                qup12, qup13, qup14, qup15, qup16, qup17, qup18, qup19, qup2,
89                qup20, qup21, qup3, qup4, qup5, qup6, qup7, qup8, qup9, qup_l4,
90                qup_l5, qup_l6, sd_write, sdc40, sdc41, sdc42, sdc43, sdc4_clk,
91                sdc4_cmd, sec_mi2s, tb_trig, tgu_ch0, tgu_ch1, tgu_ch2,
92                tgu_ch3, tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3,
93                tsense_pwm1, tsense_pwm2, uim0_clk, uim0_data, uim0_present,
94                uim0_reset, uim1_clk, uim1_data, uim1_present, uim1_reset,
95                usb2phy_ac, usb_phy, vfr_0, vfr_1, vsense_trigger ]
96
97      bias-disable: true
98      bias-pull-down: true
99      bias-pull-up: true
100      drive-strength: true
101      input-enable: true
102      output-high: true
103      output-low: true
104
105    required:
106      - pins
107      - function
108
109    additionalProperties: false
110
111examples:
112  - |
113        #include <dt-bindings/interrupt-controller/arm-gic.h>
114        pinctrl@f100000 {
115                compatible = "qcom,sm8450-tlmm";
116                reg = <0x0f100000 0x300000>;
117                gpio-controller;
118                #gpio-cells = <2>;
119                gpio-ranges = <&tlmm 0 0 211>;
120                interrupt-controller;
121                #interrupt-cells = <2>;
122                interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
123
124                gpio-wo-subnode-state {
125                        pins = "gpio1";
126                        function = "gpio";
127                };
128
129                uart-w-subnodes-state {
130                    rx {
131                            pins = "gpio26";
132                            function = "qup7";
133                            bias-pull-up;
134                    };
135
136                    tx {
137                            pins = "gpio27";
138                            function = "qup7";
139                            bias-disable;
140                    };
141               };
142        };
143...
144