1# SPDX-License-Identifier: GPL-2.0
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/rockchip,pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Rockchip Pinmux Controller
8
9maintainers:
10  - Heiko Stuebner <heiko@sntech.de>
11
12description: |
13  The Rockchip Pinmux Controller enables the IC to share one PAD
14  to several functional blocks. The sharing is done by multiplexing
15  the PAD input/output signals. For each PAD there are several muxing
16  options with option 0 being used as a GPIO.
17
18  Please refer to pinctrl-bindings.txt in this directory for details of the
19  common pinctrl bindings used by client devices, including the meaning of the
20  phrase "pin configuration node".
21
22  The Rockchip pin configuration node is a node of a group of pins which can be
23  used for a specific device or function. This node represents both mux and
24  config of the pins in that group. The 'pins' selects the function mode
25  (also named pin mode) this pin can work on and the 'config' configures
26  various pad settings such as pull-up, etc.
27
28  The pins are grouped into up to 9 individual pin banks which need to be
29  defined as gpio sub-nodes of the pinmux controller.
30
31properties:
32  compatible:
33    enum:
34      - rockchip,px30-pinctrl
35      - rockchip,rk2928-pinctrl
36      - rockchip,rk3066a-pinctrl
37      - rockchip,rk3066b-pinctrl
38      - rockchip,rk3128-pinctrl
39      - rockchip,rk3188-pinctrl
40      - rockchip,rk3228-pinctrl
41      - rockchip,rk3288-pinctrl
42      - rockchip,rk3308-pinctrl
43      - rockchip,rk3328-pinctrl
44      - rockchip,rk3368-pinctrl
45      - rockchip,rk3399-pinctrl
46      - rockchip,rk3568-pinctrl
47      - rockchip,rv1108-pinctrl
48
49  rockchip,grf:
50    $ref: "/schemas/types.yaml#/definitions/phandle"
51    description:
52      The phandle of the syscon node for the GRF registers.
53
54  rockchip,pmu:
55    $ref: "/schemas/types.yaml#/definitions/phandle"
56    description:
57      The phandle of the syscon node for the PMU registers,
58      as some SoCs carry parts of the iomux controller registers there.
59      Required for at least rk3188 and rk3288. On the rk3368 this should
60      point to the PMUGRF syscon.
61
62  "#address-cells":
63    enum: [1, 2]
64
65  "#size-cells":
66    enum: [1, 2]
67
68  ranges: true
69
70allOf:
71  - $ref: "pinctrl.yaml#"
72
73required:
74  - compatible
75  - rockchip,grf
76  - "#address-cells"
77  - "#size-cells"
78  - ranges
79
80patternProperties:
81  "gpio@[0-9a-f]+$":
82    type: object
83
84    $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#"
85
86    unevaluatedProperties: false
87
88  "pcfg-[a-z0-9-]+$":
89    type: object
90    properties:
91      bias-disable: true
92
93      bias-pull-down: true
94
95      bias-pull-pin-default: true
96
97      bias-pull-up: true
98
99      drive-strength:
100        minimum: 0
101        maximum: 20
102
103      input-enable: true
104
105      input-schmitt-enable: true
106
107      output-high: true
108
109      output-low: true
110
111    additionalProperties: false
112
113additionalProperties:
114  type: object
115  additionalProperties:
116    type: object
117    properties:
118      rockchip,pins:
119        $ref: "/schemas/types.yaml#/definitions/uint32-matrix"
120        minItems: 1
121        items:
122          items:
123            - minimum: 0
124              maximum: 8
125              description:
126                Pin bank.
127            - minimum: 0
128              maximum: 31
129              description:
130                Pin bank index.
131            - minimum: 0
132              maximum: 6
133              description:
134                Mux 0 means GPIO and mux 1 to N means
135                the specific device function.
136            - description:
137                The phandle of a node contains the generic pinconfig options
138                to use as described in pinctrl-bindings.txt.
139
140examples:
141  - |
142    #include <dt-bindings/interrupt-controller/arm-gic.h>
143    #include <dt-bindings/pinctrl/rockchip.h>
144
145    pinctrl: pinctrl {
146      compatible = "rockchip,rk3066a-pinctrl";
147      rockchip,grf = <&grf>;
148
149      #address-cells = <1>;
150      #size-cells = <1>;
151      ranges;
152
153      gpio0: gpio@20034000 {
154        compatible = "rockchip,gpio-bank";
155        reg = <0x20034000 0x100>;
156        interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
157        clocks = <&clk_gates8 9>;
158
159        gpio-controller;
160        #gpio-cells = <2>;
161
162        interrupt-controller;
163        #interrupt-cells = <2>;
164      };
165
166      pcfg_pull_default: pcfg-pull-default {
167        bias-pull-pin-default;
168      };
169
170      uart2 {
171        uart2_xfer: uart2-xfer {
172          rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>,
173                          <1 RK_PB1 1 &pcfg_pull_default>;
174        };
175      };
176    };
177
178    uart2: serial@20064000 {
179      compatible = "snps,dw-apb-uart";
180      reg = <0x20064000 0x400>;
181      interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
182      clocks = <&mux_uart2>;
183      pinctrl-0 = <&uart2_xfer>;
184      pinctrl-names = "default";
185      reg-io-width = <1>;
186      reg-shift = <2>;
187    };
188