1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2# Copyright (C) STMicroelectronics 2019.
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/pinctrl/st,stm32-pinctrl.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: STM32 GPIO and Pin Mux/Config controller
9
10maintainers:
11  - Alexandre TORGUE <alexandre.torgue@foss.st.com>
12
13description: |
14  STMicroelectronics's STM32 MCUs intregrate a GPIO and Pin mux/config hardware
15  controller. It controls the input/output settings on the available pins and
16  also provides ability to multiplex and configure the output of various
17  on-chip controllers onto these pads.
18
19properties:
20  compatible:
21    enum:
22      - st,stm32f429-pinctrl
23      - st,stm32f469-pinctrl
24      - st,stm32f746-pinctrl
25      - st,stm32f769-pinctrl
26      - st,stm32h743-pinctrl
27      - st,stm32mp135-pinctrl
28      - st,stm32mp157-pinctrl
29      - st,stm32mp157-z-pinctrl
30      - st,stm32mp257-pinctrl
31      - st,stm32mp257-z-pinctrl
32
33  '#address-cells':
34    const: 1
35  '#size-cells':
36    const: 1
37
38  ranges: true
39  pins-are-numbered:
40    $ref: /schemas/types.yaml#/definitions/flag
41    deprecated: true
42  hwlocks: true
43
44  interrupts:
45    maxItems: 1
46
47  st,syscfg:
48    description: Phandle+args to the syscon node which includes IRQ mux selection.
49    $ref: /schemas/types.yaml#/definitions/phandle-array
50    items:
51      - items:
52          - description: syscon node which includes IRQ mux selection
53          - description: The offset of the IRQ mux selection register
54          - description: The field mask of IRQ mux, needed if different of 0xf
55
56  st,package:
57    description:
58      Indicates the SOC package used.
59      More details in include/dt-bindings/pinctrl/stm32-pinfunc.h
60    $ref: /schemas/types.yaml#/definitions/uint32
61    enum: [0x1, 0x2, 0x4, 0x8, 0x100, 0x400, 0x800]
62
63patternProperties:
64  '^gpio@[0-9a-f]*$':
65    type: object
66    additionalProperties: false
67    properties:
68      gpio-controller: true
69      '#gpio-cells':
70        const: 2
71      interrupt-controller: true
72      '#interrupt-cells':
73        const: 2
74
75      reg:
76        maxItems: 1
77      clocks:
78        maxItems: 1
79      resets:
80        maxItems: 1
81      gpio-line-names: true
82      gpio-ranges:
83        minItems: 1
84        maxItems: 16
85      ngpios:
86        description:
87          Number of available gpios in a bank.
88        minimum: 1
89        maximum: 16
90
91      st,bank-name:
92        description:
93          Should be a name string for this bank as specified in the datasheet.
94        $ref: /schemas/types.yaml#/definitions/string
95        enum:
96          - GPIOA
97          - GPIOB
98          - GPIOC
99          - GPIOD
100          - GPIOE
101          - GPIOF
102          - GPIOG
103          - GPIOH
104          - GPIOI
105          - GPIOJ
106          - GPIOK
107          - GPIOZ
108
109      st,bank-ioport:
110        description:
111          Should correspond to the EXTI IOport selection (EXTI line used
112          to select GPIOs as interrupts).
113        $ref: /schemas/types.yaml#/definitions/uint32
114        minimum: 0
115        maximum: 11
116
117    patternProperties:
118      "^(.+-hog(-[0-9]+)?)$":
119        type: object
120        required:
121          - gpio-hog
122
123    required:
124      - gpio-controller
125      - '#gpio-cells'
126      - reg
127      - clocks
128      - st,bank-name
129
130  '-[0-9]*$':
131    type: object
132    additionalProperties: false
133
134    patternProperties:
135      '^pins':
136        type: object
137        additionalProperties: false
138        description: |
139          A pinctrl node should contain at least one subnode representing the
140          pinctrl group available on the machine. Each subnode will list the
141          pins it needs, and how they should be configured, with regard to muxer
142          configuration, pullups, drive, output high/low and output speed.
143        properties:
144          pinmux:
145            $ref: /schemas/types.yaml#/definitions/uint32-array
146            description: |
147              Integer array, represents gpio pin number and mux setting.
148              Supported pin number and mux varies for different SoCs, and are
149              defined in dt-bindings/pinctrl/<soc>-pinfunc.h directly.
150              These defines are calculated as: ((port * 16 + line) << 8) | function
151              With:
152              - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
153              - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
154              - function: The function number, can be:
155              * 0 : GPIO
156              * 1 : Alternate Function 0
157              * 2 : Alternate Function 1
158              * 3 : Alternate Function 2
159              * ...
160              * 16 : Alternate Function 15
161              * 17 : Analog
162              To simplify the usage, macro is available to generate "pinmux" field.
163              This macro is available here:
164                - include/dt-bindings/pinctrl/stm32-pinfunc.h
165              Some examples of using macro:
166               /* GPIO A9 set as alernate function 2 */
167               ... {
168                          pinmux = <STM32_PINMUX('A', 9, AF2)>;
169               };
170               /* GPIO A9 set as GPIO  */
171               ... {
172                          pinmux = <STM32_PINMUX('A', 9, GPIO)>;
173               };
174               /* GPIO A9 set as analog */
175               ... {
176                          pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
177               };
178
179          bias-disable:
180            type: boolean
181          bias-pull-down:
182            type: boolean
183          bias-pull-up:
184            type: boolean
185          drive-push-pull:
186            type: boolean
187          drive-open-drain:
188            type: boolean
189          output-low:
190            type: boolean
191          output-high:
192            type: boolean
193          slew-rate:
194            description: |
195              0: Low speed
196              1: Medium speed
197              2: Fast speed
198              3: High speed
199            $ref: /schemas/types.yaml#/definitions/uint32
200            enum: [0, 1, 2, 3]
201
202        required:
203          - pinmux
204
205allOf:
206  - $ref: pinctrl.yaml#
207
208required:
209  - compatible
210  - '#address-cells'
211  - '#size-cells'
212  - ranges
213
214additionalProperties: false
215
216examples:
217  - |
218    #include <dt-bindings/pinctrl/stm32-pinfunc.h>
219    #include <dt-bindings/mfd/stm32f4-rcc.h>
220    //Example 1
221      pinctrl@40020000 {
222              #address-cells = <1>;
223              #size-cells = <1>;
224              compatible = "st,stm32f429-pinctrl";
225              ranges = <0 0x40020000 0x3000>;
226
227              gpioa: gpio@0 {
228                      gpio-controller;
229                      #gpio-cells = <2>;
230                      reg = <0x0 0x400>;
231                      resets = <&reset_ahb1 0>;
232                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
233                      st,bank-name = "GPIOA";
234              };
235       };
236
237    //Example 2 (using gpio-ranges)
238      pinctrl@50020000 {
239              #address-cells = <1>;
240              #size-cells = <1>;
241              compatible = "st,stm32f429-pinctrl";
242              ranges = <0 0x50020000 0x3000>;
243
244              gpiob: gpio@1000 {
245                      gpio-controller;
246                      #gpio-cells = <2>;
247                      reg = <0x1000 0x400>;
248                      resets = <&reset_ahb1 0>;
249                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
250                      st,bank-name = "GPIOB";
251                      gpio-ranges = <&pinctrl 0 0 16>;
252              };
253
254              gpioc: gpio@2000 {
255                      gpio-controller;
256                      #gpio-cells = <2>;
257                      reg = <0x2000 0x400>;
258                      resets = <&reset_ahb1 0>;
259                      clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
260                      st,bank-name = "GPIOC";
261                      ngpios = <5>;
262                      gpio-ranges = <&pinctrl 0 16 3>,
263                                    <&pinctrl 14 30 2>;
264              };
265      };
266
267    //Example 3 pin groups
268      pinctrl {
269        usart1_pins_a: usart1-0 {
270                pins1 {
271                        pinmux = <STM32_PINMUX('A', 9, AF7)>;
272                        bias-disable;
273                        drive-push-pull;
274                        slew-rate = <0>;
275                };
276                pins2 {
277                        pinmux = <STM32_PINMUX('A', 10, AF7)>;
278                        bias-disable;
279                };
280        };
281    };
282
283    usart1 {
284                pinctrl-0 = <&usart1_pins_a>;
285                pinctrl-names = "default";
286    };
287
288...
289