1Microsemi Ocelot reset controller
2
3The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
4SoC core.
5
6The reset registers are both present in the MSCC vcoreiii MIPS and
7microchip Sparx5 armv8 SoC's.
8
9Required Properties:
10 - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset"
11
12Example:
13	reset@1070008 {
14		compatible = "mscc,ocelot-chip-reset";
15		reg = <0x1070008 0x4>;
16	};
17
18