1*c66ec88fSEmmanuel VadotPPC4xx Clock Power Management (CPM) node 2*c66ec88fSEmmanuel Vadot 3*c66ec88fSEmmanuel VadotRequired properties: 4*c66ec88fSEmmanuel Vadot - compatible : compatible list, currently only "ibm,cpm" 5*c66ec88fSEmmanuel Vadot - dcr-access-method : "native" 6*c66ec88fSEmmanuel Vadot - dcr-reg : < DCR register range > 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotOptional properties: 9*c66ec88fSEmmanuel Vadot - er-offset : All 4xx SoCs with a CPM controller have 10*c66ec88fSEmmanuel Vadot one of two different order for the CPM 11*c66ec88fSEmmanuel Vadot registers. Some have the CPM registers 12*c66ec88fSEmmanuel Vadot in the following order (ER,FR,SR). The 13*c66ec88fSEmmanuel Vadot others have them in the following order 14*c66ec88fSEmmanuel Vadot (SR,ER,FR). For the second case set 15*c66ec88fSEmmanuel Vadot er-offset = <1>. 16*c66ec88fSEmmanuel Vadot - unused-units : specifier consist of one cell. For each 17*c66ec88fSEmmanuel Vadot bit in the cell, the corresponding bit 18*c66ec88fSEmmanuel Vadot in CPM will be set to turn off unused 19*c66ec88fSEmmanuel Vadot devices. 20*c66ec88fSEmmanuel Vadot - idle-doze : specifier consist of one cell. For each 21*c66ec88fSEmmanuel Vadot bit in the cell, the corresponding bit 22*c66ec88fSEmmanuel Vadot in CPM will be set to turn off unused 23*c66ec88fSEmmanuel Vadot devices. This is usually just CPM[CPU]. 24*c66ec88fSEmmanuel Vadot - standby : specifier consist of one cell. For each 25*c66ec88fSEmmanuel Vadot bit in the cell, the corresponding bit 26*c66ec88fSEmmanuel Vadot in CPM will be set on standby and 27*c66ec88fSEmmanuel Vadot restored on resume. 28*c66ec88fSEmmanuel Vadot - suspend : specifier consist of one cell. For each 29*c66ec88fSEmmanuel Vadot bit in the cell, the corresponding bit 30*c66ec88fSEmmanuel Vadot in CPM will be set on suspend (mem) and 31*c66ec88fSEmmanuel Vadot restored on resume. Note, for standby 32*c66ec88fSEmmanuel Vadot and suspend the corresponding bits can 33*c66ec88fSEmmanuel Vadot be different or the same. Usually for 34*c66ec88fSEmmanuel Vadot standby only class 2 and 3 units are set. 35*c66ec88fSEmmanuel Vadot However, the interface does not care. 36*c66ec88fSEmmanuel Vadot If they are the same, the additional 37*c66ec88fSEmmanuel Vadot power saving will be seeing if support 38*c66ec88fSEmmanuel Vadot is available to put the DDR in self 39*c66ec88fSEmmanuel Vadot refresh mode and any additional power 40*c66ec88fSEmmanuel Vadot saving techniques for the specific SoC. 41*c66ec88fSEmmanuel Vadot 42*c66ec88fSEmmanuel VadotExample: 43*c66ec88fSEmmanuel Vadot CPM0: cpm { 44*c66ec88fSEmmanuel Vadot compatible = "ibm,cpm"; 45*c66ec88fSEmmanuel Vadot dcr-access-method = "native"; 46*c66ec88fSEmmanuel Vadot dcr-reg = <0x160 0x003>; 47*c66ec88fSEmmanuel Vadot er-offset = <0>; 48*c66ec88fSEmmanuel Vadot unused-units = <0x00000100>; 49*c66ec88fSEmmanuel Vadot idle-doze = <0x02000000>; 50*c66ec88fSEmmanuel Vadot standby = <0xfeff0000>; 51*c66ec88fSEmmanuel Vadot suspend = <0xfeff791d>; 52*c66ec88fSEmmanuel Vadot}; 53