1MediaTek display PWM controller
2
3Required properties:
4 - compatible: should be "mediatek,<name>-disp-pwm":
5   - "mediatek,mt2701-disp-pwm": found on mt2701 SoC.
6   - "mediatek,mt6595-disp-pwm": found on mt6595 SoC.
7   - "mediatek,mt8167-disp-pwm", "mediatek,mt8173-disp-pwm": found on mt8167 SoC.
8   - "mediatek,mt8173-disp-pwm": found on mt8173 SoC.
9 - reg: physical base address and length of the controller's registers.
10 - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
11   the cell format.
12 - clocks: phandle and clock specifier of the PWM reference clock.
13 - clock-names: must contain the following:
14   - "main": clock used to generate PWM signals.
15   - "mm": sync signals from the modules of mmsys.
16 - pinctrl-names: Must contain a "default" entry.
17 - pinctrl-0: One property must exist for each entry in pinctrl-names.
18   See pinctrl/pinctrl-bindings.txt for details of the property values.
19
20Example:
21	pwm0: pwm@1401e000 {
22		compatible = "mediatek,mt8173-disp-pwm",
23			     "mediatek,mt6595-disp-pwm";
24		reg = <0 0x1401e000 0 0x1000>;
25		#pwm-cells = <2>;
26		clocks = <&mmsys CLK_MM_DISP_PWM026M>,
27			 <&mmsys CLK_MM_DISP_PWM0MM>;
28		clock-names = "main", "mm";
29		pinctrl-names = "default";
30		pinctrl-0 = <&disp_pwm0_pins>;
31	};
32
33	backlight_lcd: backlight_lcd {
34		compatible = "pwm-backlight";
35		pwms = <&pwm0 0 1000000>;
36		brightness-levels = <
37			  0  16  32  48  64  80  96 112
38			128 144 160 176 192 208 224 240
39			255
40		>;
41		default-brightness-level = <9>;
42		power-supply = <&mt6397_vio18_reg>;
43		enable-gpios = <&pio 95 GPIO_ACTIVE_HIGH>;
44	};
45