1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/reset/xlnx,zynqmp-reset.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Zynq UltraScale+ MPSoC and Versal reset
8
9maintainers:
10  - Piyush Mehta <piyush.mehta@amd.com>
11
12description: |
13  The Zynq UltraScale+ MPSoC and Versal has several different resets.
14
15  The PS reset subsystem is responsible for handling the external reset
16  input to the device and that all internal reset requirements are met
17  for the system (as a whole) and for the functional units.
18
19  Please also refer to reset.txt in this directory for common reset
20  controller binding usage. Device nodes that need access to reset
21  lines should specify them as a reset phandle in their corresponding
22  node as specified in reset.txt.
23
24  For list of all valid reset indices for Zynq UltraScale+ MPSoC
25  <dt-bindings/reset/xlnx-zynqmp-resets.h>
26
27  For list of all valid reset indices for Versal
28  <dt-bindings/reset/xlnx-versal-resets.h>
29
30properties:
31  compatible:
32    enum:
33      - xlnx,zynqmp-reset
34      - xlnx,versal-reset
35      - xlnx,versal-net-reset
36
37  "#reset-cells":
38    const: 1
39
40required:
41  - compatible
42  - "#reset-cells"
43
44additionalProperties: false
45
46examples:
47  - |
48    zynqmp_reset: reset-controller {
49        compatible = "xlnx,zynqmp-reset";
50        #reset-cells = <1>;
51    };
52
53...
54