1c66ec88fSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2c66ec88fSEmmanuel Vadot%YAML 1.2 3c66ec88fSEmmanuel Vadot--- 4c66ec88fSEmmanuel Vadot$id: http://devicetree.org/schemas/riscv/cpus.yaml# 5c66ec88fSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6c66ec88fSEmmanuel Vadot 78bab661aSEmmanuel Vadottitle: RISC-V CPUs 8c66ec88fSEmmanuel Vadot 9c66ec88fSEmmanuel Vadotmaintainers: 10c66ec88fSEmmanuel Vadot - Paul Walmsley <paul.walmsley@sifive.com> 11c66ec88fSEmmanuel Vadot - Palmer Dabbelt <palmer@sifive.com> 127ef62cebSEmmanuel Vadot - Conor Dooley <conor@kernel.org> 13c66ec88fSEmmanuel Vadot 14c66ec88fSEmmanuel Vadotdescription: | 15c66ec88fSEmmanuel Vadot This document uses some terminology common to the RISC-V community 16c66ec88fSEmmanuel Vadot that is not widely used, the definitions of which are listed here: 17c66ec88fSEmmanuel Vadot 18c66ec88fSEmmanuel Vadot hart: A hardware execution context, which contains all the state 19c66ec88fSEmmanuel Vadot mandated by the RISC-V ISA: a PC and some registers. This 20c66ec88fSEmmanuel Vadot terminology is designed to disambiguate software's view of execution 21c66ec88fSEmmanuel Vadot contexts from any particular microarchitectural implementation 22c66ec88fSEmmanuel Vadot strategy. For example, an Intel laptop containing one socket with 23c66ec88fSEmmanuel Vadot two cores, each of which has two hyperthreads, could be described as 24c66ec88fSEmmanuel Vadot having four harts. 25c66ec88fSEmmanuel Vadot 26*f126890aSEmmanuel VadotallOf: 27*f126890aSEmmanuel Vadot - $ref: /schemas/cpu.yaml# 28*f126890aSEmmanuel Vadot - $ref: extensions.yaml 29*f126890aSEmmanuel Vadot 30c66ec88fSEmmanuel Vadotproperties: 31c66ec88fSEmmanuel Vadot compatible: 32c66ec88fSEmmanuel Vadot oneOf: 33c66ec88fSEmmanuel Vadot - items: 34c66ec88fSEmmanuel Vadot - enum: 358bab661aSEmmanuel Vadot - andestech,ax45mp 368bab661aSEmmanuel Vadot - canaan,k210 375def4c47SEmmanuel Vadot - sifive,bullet0 38c66ec88fSEmmanuel Vadot - sifive,e5 395def4c47SEmmanuel Vadot - sifive,e7 405def4c47SEmmanuel Vadot - sifive,e71 418bab661aSEmmanuel Vadot - sifive,rocket0 42fac71e4eSEmmanuel Vadot - sifive,s7 43c66ec88fSEmmanuel Vadot - sifive,u5 448bab661aSEmmanuel Vadot - sifive,u54 455def4c47SEmmanuel Vadot - sifive,u7 468bab661aSEmmanuel Vadot - sifive,u74 478bab661aSEmmanuel Vadot - sifive,u74-mc 488bab661aSEmmanuel Vadot - thead,c906 498bab661aSEmmanuel Vadot - thead,c910 50c66ec88fSEmmanuel Vadot - const: riscv 518cc087a1SEmmanuel Vadot - items: 528cc087a1SEmmanuel Vadot - enum: 538cc087a1SEmmanuel Vadot - sifive,e51 548cc087a1SEmmanuel Vadot - sifive,u54-mc 558cc087a1SEmmanuel Vadot - const: sifive,rocket0 568cc087a1SEmmanuel Vadot - const: riscv 57c66ec88fSEmmanuel Vadot - const: riscv # Simulator only 58c66ec88fSEmmanuel Vadot description: 59c66ec88fSEmmanuel Vadot Identifies that the hart uses the RISC-V instruction set 60c66ec88fSEmmanuel Vadot and identifies the type of the hart. 61c66ec88fSEmmanuel Vadot 62c66ec88fSEmmanuel Vadot mmu-type: 63c66ec88fSEmmanuel Vadot description: 64c66ec88fSEmmanuel Vadot Identifies the MMU address translation mode used on this 65c66ec88fSEmmanuel Vadot hart. These values originate from the RISC-V Privileged 66c66ec88fSEmmanuel Vadot Specification document, available from 67c66ec88fSEmmanuel Vadot https://riscv.org/specifications/ 68*f126890aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/string 69c66ec88fSEmmanuel Vadot enum: 70c66ec88fSEmmanuel Vadot - riscv,sv32 71c66ec88fSEmmanuel Vadot - riscv,sv39 72c66ec88fSEmmanuel Vadot - riscv,sv48 73fac71e4eSEmmanuel Vadot - riscv,sv57 745def4c47SEmmanuel Vadot - riscv,none 75c66ec88fSEmmanuel Vadot 76b97ee269SEmmanuel Vadot riscv,cbom-block-size: 77b97ee269SEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 78b97ee269SEmmanuel Vadot description: 79b97ee269SEmmanuel Vadot The blocksize in bytes for the Zicbom cache operations. 80b97ee269SEmmanuel Vadot 81fac71e4eSEmmanuel Vadot riscv,cboz-block-size: 82fac71e4eSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/uint32 83fac71e4eSEmmanuel Vadot description: 84fac71e4eSEmmanuel Vadot The blocksize in bytes for the Zicboz cache operations. 85fac71e4eSEmmanuel Vadot 86*f126890aSEmmanuel Vadot # RISC-V has multiple properties for cache op block sizes as the sizes 87*f126890aSEmmanuel Vadot # differ between individual CBO extensions 88*f126890aSEmmanuel Vadot cache-op-block-size: false 89c66ec88fSEmmanuel Vadot # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here 90c66ec88fSEmmanuel Vadot timebase-frequency: false 91c66ec88fSEmmanuel Vadot 92c66ec88fSEmmanuel Vadot interrupt-controller: 93c66ec88fSEmmanuel Vadot type: object 94c66ec88fSEmmanuel Vadot description: Describes the CPU's local interrupt controller 95c66ec88fSEmmanuel Vadot 96c66ec88fSEmmanuel Vadot properties: 97c66ec88fSEmmanuel Vadot '#interrupt-cells': 98c66ec88fSEmmanuel Vadot const: 1 99c66ec88fSEmmanuel Vadot 100c66ec88fSEmmanuel Vadot compatible: 101c66ec88fSEmmanuel Vadot const: riscv,cpu-intc 102c66ec88fSEmmanuel Vadot 103c66ec88fSEmmanuel Vadot interrupt-controller: true 104c66ec88fSEmmanuel Vadot 105c66ec88fSEmmanuel Vadot required: 106c66ec88fSEmmanuel Vadot - '#interrupt-cells' 107c66ec88fSEmmanuel Vadot - compatible 108c66ec88fSEmmanuel Vadot - interrupt-controller 109c66ec88fSEmmanuel Vadot 110c9ccf3a3SEmmanuel Vadot cpu-idle-states: 111*f126890aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/phandle-array 112c9ccf3a3SEmmanuel Vadot items: 113c9ccf3a3SEmmanuel Vadot maxItems: 1 114c9ccf3a3SEmmanuel Vadot description: | 115c9ccf3a3SEmmanuel Vadot List of phandles to idle state nodes supported 116c9ccf3a3SEmmanuel Vadot by this hart (see ./idle-states.yaml). 117c9ccf3a3SEmmanuel Vadot 118cb7aa33aSEmmanuel Vadot capacity-dmips-mhz: 119cb7aa33aSEmmanuel Vadot description: 120cb7aa33aSEmmanuel Vadot u32 value representing CPU capacity (see ../cpu/cpu-capacity.txt) in 121cb7aa33aSEmmanuel Vadot DMIPS/MHz, relative to highest capacity-dmips-mhz 122cb7aa33aSEmmanuel Vadot in the system. 123cb7aa33aSEmmanuel Vadot 124*f126890aSEmmanuel VadotanyOf: 125*f126890aSEmmanuel Vadot - required: 126c66ec88fSEmmanuel Vadot - riscv,isa 127*f126890aSEmmanuel Vadot - required: 128*f126890aSEmmanuel Vadot - riscv,isa-base 129*f126890aSEmmanuel Vadot 130*f126890aSEmmanuel Vadotdependencies: 131*f126890aSEmmanuel Vadot riscv,isa-base: [ "riscv,isa-extensions" ] 132*f126890aSEmmanuel Vadot riscv,isa-extensions: [ "riscv,isa-base" ] 133*f126890aSEmmanuel Vadot 134*f126890aSEmmanuel Vadotrequired: 135c66ec88fSEmmanuel Vadot - interrupt-controller 136c66ec88fSEmmanuel Vadot 137*f126890aSEmmanuel VadotunevaluatedProperties: false 1386be33864SEmmanuel Vadot 139c66ec88fSEmmanuel Vadotexamples: 140c66ec88fSEmmanuel Vadot - | 141c66ec88fSEmmanuel Vadot // Example 1: SiFive Freedom U540G Development Kit 142c66ec88fSEmmanuel Vadot cpus { 143c66ec88fSEmmanuel Vadot #address-cells = <1>; 144c66ec88fSEmmanuel Vadot #size-cells = <0>; 145c66ec88fSEmmanuel Vadot timebase-frequency = <1000000>; 146c66ec88fSEmmanuel Vadot cpu@0 { 147c66ec88fSEmmanuel Vadot clock-frequency = <0>; 148c66ec88fSEmmanuel Vadot compatible = "sifive,rocket0", "riscv"; 149c66ec88fSEmmanuel Vadot device_type = "cpu"; 150c66ec88fSEmmanuel Vadot i-cache-block-size = <64>; 151c66ec88fSEmmanuel Vadot i-cache-sets = <128>; 152c66ec88fSEmmanuel Vadot i-cache-size = <16384>; 153c66ec88fSEmmanuel Vadot reg = <0>; 154*f126890aSEmmanuel Vadot riscv,isa-base = "rv64i"; 155*f126890aSEmmanuel Vadot riscv,isa-extensions = "i", "m", "a", "c"; 156*f126890aSEmmanuel Vadot 157c66ec88fSEmmanuel Vadot cpu_intc0: interrupt-controller { 158c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 159c66ec88fSEmmanuel Vadot compatible = "riscv,cpu-intc"; 160c66ec88fSEmmanuel Vadot interrupt-controller; 161c66ec88fSEmmanuel Vadot }; 162c66ec88fSEmmanuel Vadot }; 163c66ec88fSEmmanuel Vadot cpu@1 { 164c66ec88fSEmmanuel Vadot clock-frequency = <0>; 165c66ec88fSEmmanuel Vadot compatible = "sifive,rocket0", "riscv"; 166c66ec88fSEmmanuel Vadot d-cache-block-size = <64>; 167c66ec88fSEmmanuel Vadot d-cache-sets = <64>; 168c66ec88fSEmmanuel Vadot d-cache-size = <32768>; 169c66ec88fSEmmanuel Vadot d-tlb-sets = <1>; 170c66ec88fSEmmanuel Vadot d-tlb-size = <32>; 171c66ec88fSEmmanuel Vadot device_type = "cpu"; 172c66ec88fSEmmanuel Vadot i-cache-block-size = <64>; 173c66ec88fSEmmanuel Vadot i-cache-sets = <64>; 174c66ec88fSEmmanuel Vadot i-cache-size = <32768>; 175c66ec88fSEmmanuel Vadot i-tlb-sets = <1>; 176c66ec88fSEmmanuel Vadot i-tlb-size = <32>; 177c66ec88fSEmmanuel Vadot mmu-type = "riscv,sv39"; 178c66ec88fSEmmanuel Vadot reg = <1>; 179c66ec88fSEmmanuel Vadot tlb-split; 180*f126890aSEmmanuel Vadot riscv,isa-base = "rv64i"; 181*f126890aSEmmanuel Vadot riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 182*f126890aSEmmanuel Vadot 183c66ec88fSEmmanuel Vadot cpu_intc1: interrupt-controller { 184c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 185c66ec88fSEmmanuel Vadot compatible = "riscv,cpu-intc"; 186c66ec88fSEmmanuel Vadot interrupt-controller; 187c66ec88fSEmmanuel Vadot }; 188c66ec88fSEmmanuel Vadot }; 189c66ec88fSEmmanuel Vadot }; 190c66ec88fSEmmanuel Vadot 191c66ec88fSEmmanuel Vadot - | 192c66ec88fSEmmanuel Vadot // Example 2: Spike ISA Simulator with 1 Hart 193c66ec88fSEmmanuel Vadot cpus { 194c66ec88fSEmmanuel Vadot #address-cells = <1>; 195c66ec88fSEmmanuel Vadot #size-cells = <0>; 196c66ec88fSEmmanuel Vadot cpu@0 { 197c66ec88fSEmmanuel Vadot device_type = "cpu"; 198c66ec88fSEmmanuel Vadot reg = <0>; 199c66ec88fSEmmanuel Vadot compatible = "riscv"; 200c66ec88fSEmmanuel Vadot mmu-type = "riscv,sv48"; 201*f126890aSEmmanuel Vadot riscv,isa-base = "rv64i"; 202*f126890aSEmmanuel Vadot riscv,isa-extensions = "i", "m", "a", "f", "d", "c"; 203*f126890aSEmmanuel Vadot 204c66ec88fSEmmanuel Vadot interrupt-controller { 205c66ec88fSEmmanuel Vadot #interrupt-cells = <1>; 206c66ec88fSEmmanuel Vadot interrupt-controller; 207c66ec88fSEmmanuel Vadot compatible = "riscv,cpu-intc"; 208c66ec88fSEmmanuel Vadot }; 209c66ec88fSEmmanuel Vadot }; 210c66ec88fSEmmanuel Vadot }; 211c66ec88fSEmmanuel Vadot... 212