1*f126890aSEmmanuel Vadot# SPDX-License-Identifier: (GPL-2.0 OR MIT) 2*f126890aSEmmanuel Vadot%YAML 1.2 3*f126890aSEmmanuel Vadot--- 4*f126890aSEmmanuel Vadot$id: http://devicetree.org/schemas/riscv/extensions.yaml# 5*f126890aSEmmanuel Vadot$schema: http://devicetree.org/meta-schemas/core.yaml# 6*f126890aSEmmanuel Vadot 7*f126890aSEmmanuel Vadottitle: RISC-V ISA extensions 8*f126890aSEmmanuel Vadot 9*f126890aSEmmanuel Vadotmaintainers: 10*f126890aSEmmanuel Vadot - Paul Walmsley <paul.walmsley@sifive.com> 11*f126890aSEmmanuel Vadot - Palmer Dabbelt <palmer@sifive.com> 12*f126890aSEmmanuel Vadot - Conor Dooley <conor@kernel.org> 13*f126890aSEmmanuel Vadot 14*f126890aSEmmanuel Vadotdescription: | 15*f126890aSEmmanuel Vadot RISC-V has a large number of extensions, some of which are "standard" 16*f126890aSEmmanuel Vadot extensions, meaning they are ratified by RISC-V International, and others 17*f126890aSEmmanuel Vadot are "vendor" extensions. 18*f126890aSEmmanuel Vadot This document defines properties that indicate whether a hart supports a 19*f126890aSEmmanuel Vadot given extension. 20*f126890aSEmmanuel Vadot 21*f126890aSEmmanuel Vadot Once a standard extension has been ratified, no changes in behaviour can be 22*f126890aSEmmanuel Vadot made without the creation of a new extension. 23*f126890aSEmmanuel Vadot The properties for standard extensions therefore map to their originally 24*f126890aSEmmanuel Vadot ratified states, with the exception of the I, Zicntr & Zihpm extensions. 25*f126890aSEmmanuel Vadot See the "i" property for more information. 26*f126890aSEmmanuel Vadot 27*f126890aSEmmanuel Vadotselect: 28*f126890aSEmmanuel Vadot properties: 29*f126890aSEmmanuel Vadot compatible: 30*f126890aSEmmanuel Vadot contains: 31*f126890aSEmmanuel Vadot const: riscv 32*f126890aSEmmanuel Vadot 33*f126890aSEmmanuel Vadotproperties: 34*f126890aSEmmanuel Vadot riscv,isa: 35*f126890aSEmmanuel Vadot description: 36*f126890aSEmmanuel Vadot Identifies the specific RISC-V instruction set architecture 37*f126890aSEmmanuel Vadot supported by the hart. These are documented in the RISC-V 38*f126890aSEmmanuel Vadot User-Level ISA document, available from 39*f126890aSEmmanuel Vadot https://riscv.org/specifications/ 40*f126890aSEmmanuel Vadot 41*f126890aSEmmanuel Vadot Due to revisions of the ISA specification, some deviations 42*f126890aSEmmanuel Vadot have arisen over time. 43*f126890aSEmmanuel Vadot Notably, riscv,isa was defined prior to the creation of the 44*f126890aSEmmanuel Vadot Zicntr, Zicsr, Zifencei and Zihpm extensions and thus "i" 45*f126890aSEmmanuel Vadot implies "zicntr_zicsr_zifencei_zihpm". 46*f126890aSEmmanuel Vadot 47*f126890aSEmmanuel Vadot While the isa strings in ISA specification are case 48*f126890aSEmmanuel Vadot insensitive, letters in the riscv,isa string must be all 49*f126890aSEmmanuel Vadot lowercase. 50*f126890aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/string 51*f126890aSEmmanuel Vadot pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ 52*f126890aSEmmanuel Vadot deprecated: true 53*f126890aSEmmanuel Vadot 54*f126890aSEmmanuel Vadot riscv,isa-base: 55*f126890aSEmmanuel Vadot description: 56*f126890aSEmmanuel Vadot The base ISA implemented by this hart, as described by the 20191213 57*f126890aSEmmanuel Vadot version of the unprivileged ISA specification. 58*f126890aSEmmanuel Vadot enum: 59*f126890aSEmmanuel Vadot - rv32i 60*f126890aSEmmanuel Vadot - rv64i 61*f126890aSEmmanuel Vadot 62*f126890aSEmmanuel Vadot riscv,isa-extensions: 63*f126890aSEmmanuel Vadot $ref: /schemas/types.yaml#/definitions/string-array 64*f126890aSEmmanuel Vadot minItems: 1 65*f126890aSEmmanuel Vadot description: Extensions supported by the hart. 66*f126890aSEmmanuel Vadot items: 67*f126890aSEmmanuel Vadot anyOf: 68*f126890aSEmmanuel Vadot # single letter extensions, in canonical order 69*f126890aSEmmanuel Vadot - const: i 70*f126890aSEmmanuel Vadot description: | 71*f126890aSEmmanuel Vadot The base integer instruction set, as ratified in the 20191213 72*f126890aSEmmanuel Vadot version of the unprivileged ISA specification. 73*f126890aSEmmanuel Vadot 74*f126890aSEmmanuel Vadot This does not include Chapter 10, "Counters", which was moved into 75*f126890aSEmmanuel Vadot the Zicntr and Zihpm extensions after the ratification of the 76*f126890aSEmmanuel Vadot 20191213 version of the unprivileged specification. 77*f126890aSEmmanuel Vadot 78*f126890aSEmmanuel Vadot - const: m 79*f126890aSEmmanuel Vadot description: 80*f126890aSEmmanuel Vadot The standard M extension for integer multiplication and division, as 81*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 82*f126890aSEmmanuel Vadot specification. 83*f126890aSEmmanuel Vadot 84*f126890aSEmmanuel Vadot - const: a 85*f126890aSEmmanuel Vadot description: 86*f126890aSEmmanuel Vadot The standard A extension for atomic instructions, as ratified in the 87*f126890aSEmmanuel Vadot 20191213 version of the unprivileged ISA specification. 88*f126890aSEmmanuel Vadot 89*f126890aSEmmanuel Vadot - const: f 90*f126890aSEmmanuel Vadot description: 91*f126890aSEmmanuel Vadot The standard F extension for single-precision floating point, as 92*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 93*f126890aSEmmanuel Vadot specification. 94*f126890aSEmmanuel Vadot 95*f126890aSEmmanuel Vadot - const: d 96*f126890aSEmmanuel Vadot description: 97*f126890aSEmmanuel Vadot The standard D extension for double-precision floating-point, as 98*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 99*f126890aSEmmanuel Vadot specification. 100*f126890aSEmmanuel Vadot 101*f126890aSEmmanuel Vadot - const: q 102*f126890aSEmmanuel Vadot description: 103*f126890aSEmmanuel Vadot The standard Q extension for quad-precision floating-point, as 104*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 105*f126890aSEmmanuel Vadot specification. 106*f126890aSEmmanuel Vadot 107*f126890aSEmmanuel Vadot - const: c 108*f126890aSEmmanuel Vadot description: 109*f126890aSEmmanuel Vadot The standard C extension for compressed instructions, as ratified in 110*f126890aSEmmanuel Vadot the 20191213 version of the unprivileged ISA specification. 111*f126890aSEmmanuel Vadot 112*f126890aSEmmanuel Vadot - const: v 113*f126890aSEmmanuel Vadot description: 114*f126890aSEmmanuel Vadot The standard V extension for vector operations, as ratified 115*f126890aSEmmanuel Vadot in-and-around commit 7a6c8ae ("Fix text that describes vfmv.v.f 116*f126890aSEmmanuel Vadot encoding") of the riscv-v-spec. 117*f126890aSEmmanuel Vadot 118*f126890aSEmmanuel Vadot - const: h 119*f126890aSEmmanuel Vadot description: 120*f126890aSEmmanuel Vadot The standard H extension for hypervisors as ratified in the 20191213 121*f126890aSEmmanuel Vadot version of the privileged ISA specification. 122*f126890aSEmmanuel Vadot 123*f126890aSEmmanuel Vadot # multi-letter extensions, sorted alphanumerically 124*f126890aSEmmanuel Vadot - const: smaia 125*f126890aSEmmanuel Vadot description: | 126*f126890aSEmmanuel Vadot The standard Smaia supervisor-level extension for the advanced 127*f126890aSEmmanuel Vadot interrupt architecture for machine-mode-visible csr and behavioural 128*f126890aSEmmanuel Vadot changes to interrupts as frozen at commit ccbddab ("Merge pull 129*f126890aSEmmanuel Vadot request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 130*f126890aSEmmanuel Vadot 131*f126890aSEmmanuel Vadot - const: ssaia 132*f126890aSEmmanuel Vadot description: | 133*f126890aSEmmanuel Vadot The standard Ssaia supervisor-level extension for the advanced 134*f126890aSEmmanuel Vadot interrupt architecture for supervisor-mode-visible csr and 135*f126890aSEmmanuel Vadot behavioural changes to interrupts as frozen at commit ccbddab 136*f126890aSEmmanuel Vadot ("Merge pull request #42 from riscv/jhauser-2023-RC4") of riscv-aia. 137*f126890aSEmmanuel Vadot 138*f126890aSEmmanuel Vadot - const: sscofpmf 139*f126890aSEmmanuel Vadot description: | 140*f126890aSEmmanuel Vadot The standard Sscofpmf supervisor-level extension for count overflow 141*f126890aSEmmanuel Vadot and mode-based filtering as ratified at commit 01d1df0 ("Add ability 142*f126890aSEmmanuel Vadot to manually trigger workflow. (#2)") of riscv-count-overflow. 143*f126890aSEmmanuel Vadot 144*f126890aSEmmanuel Vadot - const: sstc 145*f126890aSEmmanuel Vadot description: | 146*f126890aSEmmanuel Vadot The standard Sstc supervisor-level extension for time compare as 147*f126890aSEmmanuel Vadot ratified at commit 3f9ed34 ("Add ability to manually trigger 148*f126890aSEmmanuel Vadot workflow. (#2)") of riscv-time-compare. 149*f126890aSEmmanuel Vadot 150*f126890aSEmmanuel Vadot - const: svinval 151*f126890aSEmmanuel Vadot description: 152*f126890aSEmmanuel Vadot The standard Svinval supervisor-level extension for fine-grained 153*f126890aSEmmanuel Vadot address-translation cache invalidation as ratified in the 20191213 154*f126890aSEmmanuel Vadot version of the privileged ISA specification. 155*f126890aSEmmanuel Vadot 156*f126890aSEmmanuel Vadot - const: svnapot 157*f126890aSEmmanuel Vadot description: 158*f126890aSEmmanuel Vadot The standard Svnapot supervisor-level extensions for napot 159*f126890aSEmmanuel Vadot translation contiguity as ratified in the 20191213 version of the 160*f126890aSEmmanuel Vadot privileged ISA specification. 161*f126890aSEmmanuel Vadot 162*f126890aSEmmanuel Vadot - const: svpbmt 163*f126890aSEmmanuel Vadot description: 164*f126890aSEmmanuel Vadot The standard Svpbmt supervisor-level extensions for page-based 165*f126890aSEmmanuel Vadot memory types as ratified in the 20191213 version of the privileged 166*f126890aSEmmanuel Vadot ISA specification. 167*f126890aSEmmanuel Vadot 168*f126890aSEmmanuel Vadot - const: zba 169*f126890aSEmmanuel Vadot description: | 170*f126890aSEmmanuel Vadot The standard Zba bit-manipulation extension for address generation 171*f126890aSEmmanuel Vadot acceleration instructions as ratified at commit 6d33919 ("Merge pull 172*f126890aSEmmanuel Vadot request #158 from hirooih/clmul-fix-loop-end-condition") of 173*f126890aSEmmanuel Vadot riscv-bitmanip. 174*f126890aSEmmanuel Vadot 175*f126890aSEmmanuel Vadot - const: zbb 176*f126890aSEmmanuel Vadot description: | 177*f126890aSEmmanuel Vadot The standard Zbb bit-manipulation extension for basic bit-manipulation 178*f126890aSEmmanuel Vadot as ratified at commit 6d33919 ("Merge pull request #158 from 179*f126890aSEmmanuel Vadot hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 180*f126890aSEmmanuel Vadot 181*f126890aSEmmanuel Vadot - const: zbc 182*f126890aSEmmanuel Vadot description: | 183*f126890aSEmmanuel Vadot The standard Zbc bit-manipulation extension for carry-less 184*f126890aSEmmanuel Vadot multiplication as ratified at commit 6d33919 ("Merge pull request 185*f126890aSEmmanuel Vadot #158 from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 186*f126890aSEmmanuel Vadot 187*f126890aSEmmanuel Vadot - const: zbs 188*f126890aSEmmanuel Vadot description: | 189*f126890aSEmmanuel Vadot The standard Zbs bit-manipulation extension for single-bit 190*f126890aSEmmanuel Vadot instructions as ratified at commit 6d33919 ("Merge pull request #158 191*f126890aSEmmanuel Vadot from hirooih/clmul-fix-loop-end-condition") of riscv-bitmanip. 192*f126890aSEmmanuel Vadot 193*f126890aSEmmanuel Vadot - const: zicbom 194*f126890aSEmmanuel Vadot description: 195*f126890aSEmmanuel Vadot The standard Zicbom extension for base cache management operations as 196*f126890aSEmmanuel Vadot ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 197*f126890aSEmmanuel Vadot 198*f126890aSEmmanuel Vadot - const: zicbop 199*f126890aSEmmanuel Vadot description: 200*f126890aSEmmanuel Vadot The standard Zicbop extension for cache-block prefetch instructions 201*f126890aSEmmanuel Vadot as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of 202*f126890aSEmmanuel Vadot riscv-CMOs. 203*f126890aSEmmanuel Vadot 204*f126890aSEmmanuel Vadot - const: zicboz 205*f126890aSEmmanuel Vadot description: 206*f126890aSEmmanuel Vadot The standard Zicboz extension for cache-block zeroing as ratified 207*f126890aSEmmanuel Vadot in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. 208*f126890aSEmmanuel Vadot 209*f126890aSEmmanuel Vadot - const: zicntr 210*f126890aSEmmanuel Vadot description: 211*f126890aSEmmanuel Vadot The standard Zicntr extension for base counters and timers, as 212*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 213*f126890aSEmmanuel Vadot specification. 214*f126890aSEmmanuel Vadot 215*f126890aSEmmanuel Vadot - const: zicsr 216*f126890aSEmmanuel Vadot description: | 217*f126890aSEmmanuel Vadot The standard Zicsr extension for control and status register 218*f126890aSEmmanuel Vadot instructions, as ratified in the 20191213 version of the 219*f126890aSEmmanuel Vadot unprivileged ISA specification. 220*f126890aSEmmanuel Vadot 221*f126890aSEmmanuel Vadot This does not include Chapter 10, "Counters", which documents 222*f126890aSEmmanuel Vadot special case read-only CSRs, that were moved into the Zicntr and 223*f126890aSEmmanuel Vadot Zihpm extensions after the ratification of the 20191213 version of 224*f126890aSEmmanuel Vadot the unprivileged specification. 225*f126890aSEmmanuel Vadot 226*f126890aSEmmanuel Vadot - const: zifencei 227*f126890aSEmmanuel Vadot description: 228*f126890aSEmmanuel Vadot The standard Zifencei extension for instruction-fetch fence, as 229*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 230*f126890aSEmmanuel Vadot specification. 231*f126890aSEmmanuel Vadot 232*f126890aSEmmanuel Vadot - const: zihintpause 233*f126890aSEmmanuel Vadot description: 234*f126890aSEmmanuel Vadot The standard Zihintpause extension for pause hints, as ratified in 235*f126890aSEmmanuel Vadot commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. 236*f126890aSEmmanuel Vadot 237*f126890aSEmmanuel Vadot - const: zihpm 238*f126890aSEmmanuel Vadot description: 239*f126890aSEmmanuel Vadot The standard Zihpm extension for hardware performance counters, as 240*f126890aSEmmanuel Vadot ratified in the 20191213 version of the unprivileged ISA 241*f126890aSEmmanuel Vadot specification. 242*f126890aSEmmanuel Vadot 243*f126890aSEmmanuel Vadot - const: ztso 244*f126890aSEmmanuel Vadot description: 245*f126890aSEmmanuel Vadot The standard Ztso extension for total store ordering, as ratified 246*f126890aSEmmanuel Vadot in commit 2e5236 ("Ztso is now ratified.") of the 247*f126890aSEmmanuel Vadot riscv-isa-manual. 248*f126890aSEmmanuel Vadot 249*f126890aSEmmanuel VadotadditionalProperties: true 250*f126890aSEmmanuel Vadot... 251