1Device tree bindings for Marvell PXA SSP ports
2
3Required properties:
4
5	- compatible:	Must be one of
6				mrvl,pxa25x-ssp
7				mvrl,pxa25x-nssp
8				mrvl,pxa27x-ssp
9				mrvl,pxa3xx-ssp
10				mvrl,pxa168-ssp
11				mrvl,pxa910-ssp
12				mrvl,ce4100-ssp
13
14	- reg:		The memory base
15	- dmas:		Two dma phandles, one for rx, one for tx
16	- dma-names:	Must be "rx", "tx"
17
18
19Example for PXA3xx:
20
21	ssp0: ssp@41000000 {
22		compatible = "mrvl,pxa3xx-ssp";
23		reg = <0x41000000 0x40>;
24		ssp-id = <1>;
25		interrupts = <24>;
26		clock-names = "pxa27x-ssp.0";
27		dmas = <&dma 13
28			&dma 14>;
29		dma-names = "rx", "tx";
30	};
31
32	ssp1: ssp@41700000 {
33		compatible = "mrvl,pxa3xx-ssp";
34		reg = <0x41700000 0x40>;
35		ssp-id = <2>;
36		interrupts = <16>;
37		clock-names = "pxa27x-ssp.1";
38		dmas = <&dma 15
39			&dma 16>;
40		dma-names = "rx", "tx";
41	};
42
43	ssp2: ssp@41900000 {
44		compatibl3 = "mrvl,pxa3xx-ssp";
45		reg = <0x41900000 0x40>;
46		ssp-id = <3>;
47		interrupts = <0>;
48		clock-names = "pxa27x-ssp.2";
49		dmas = <&dma 66
50			&dma 67>;
51		dma-names = "rx", "tx";
52	};
53
54	ssp3: ssp@41a00000 {
55		compatible = "mrvl,pxa3xx-ssp";
56		reg = <0x41a00000 0x40>;
57		ssp-id = <4>;
58		interrupts = <13>;
59		clock-names = "pxa27x-ssp.3";
60		dmas = <&dma 2
61			&dma 3>;
62		dma-names = "rx", "tx";
63	};
64
65