1Xilinx Axi Uartlite controller Device Tree Bindings
2---------------------------------------------------------
3
4Required properties:
5- compatible		: Can be either of
6				"xlnx,xps-uartlite-1.00.a"
7				"xlnx,opb-uartlite-1.00.b"
8- reg			: Physical base address and size of the Axi Uartlite
9			  registers map.
10- interrupts		: Should contain the UART controller interrupt.
11
12Optional properties:
13- port-number		: Set Uart port number
14- clock-names		: Should be "s_axi_aclk"
15- clocks		: Input clock specifier. Refer to common clock bindings.
16
17Example:
18serial@800c0000 {
19	compatible = "xlnx,xps-uartlite-1.00.a";
20	reg = <0x0 0x800c0000 0x10000>;
21	interrupts = <0x0 0x6e 0x1>;
22	port-number = <0>;
23};
24