1Freescale Synchronous Audio Interface (SAI).
2
3The SAI is based on I2S module that used communicating with audio codecs,
4which provides a synchronous audio interface that supports fullduplex
5serial interfaces with frame synchronization such as I2S, AC97, TDM, and
6codec/DSP interfaces.
7
8Required properties:
9
10  - compatible		: Compatible list, contains "fsl,vf610-sai",
11			  "fsl,imx6sx-sai", "fsl,imx6ul-sai",
12			  "fsl,imx7ulp-sai", "fsl,imx8mq-sai",
13			  "fsl,imx8qm-sai", "fsl,imx8mm-sai",
14			  "fsl,imx8mn-sai", "fsl,imx8mp-sai", or
15			  "fsl,imx8ulp-sai".
16
17  - reg			: Offset and length of the register set for the device.
18
19  - clocks		: Must contain an entry for each entry in clock-names.
20
21  - clock-names		: Must include the "bus" for register access and
22			  "mclk1", "mclk2", "mclk3" for bit clock and frame
23			  clock providing.
24                          "pll8k", "pll11k" are optional, they are the clock
25                          source for root clock, one is for 8kHz series rates
26                          another one is for 11kHz series rates.
27  - dmas		: Generic dma devicetree binding as described in
28			  Documentation/devicetree/bindings/dma/dma.txt.
29
30  - dma-names		: Two dmas have to be defined, "tx" and "rx".
31
32  - pinctrl-names	: Must contain a "default" entry.
33
34  - pinctrl-NNN		: One property must exist for each entry in
35			  pinctrl-names. See ../pinctrl/pinctrl-bindings.txt
36			  for details of the property values.
37
38  - lsb-first		: Configures whether the LSB or the MSB is transmitted
39			  first for the fifo data. If this property is absent,
40			  the MSB is transmitted first as default, or the LSB
41			  is transmitted first.
42
43  - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating
44			  that SAI will work in the synchronous mode (sync Tx
45			  with Rx) which means both the transmitter and the
46			  receiver will send and receive data by following
47			  receiver's bit clocks and frame sync clocks.
48
49  - fsl,sai-asynchronous: This is a boolean property. If present, indicating
50			  that SAI will work in the asynchronous mode, which
51			  means both transmitter and receiver will send and
52			  receive data by following their own bit clocks and
53			  frame sync clocks separately.
54
55  - fsl,dataline        : configure the dataline. it has 3 value for each configuration
56                          first one means the type: I2S(1) or PDM(2)
57                          second one is dataline mask for 'rx'
58                          third one is dataline mask for 'tx'.
59                          for example: fsl,dataline = <1 0xff 0xff 2 0xff 0x11>;
60                          it means I2S type rx mask is 0xff, tx mask is 0xff, PDM type
61                          rx mask is 0xff, tx mask is 0x11 (dataline 1 and 4 enabled).
62
63Optional properties:
64
65  - big-endian		: Boolean property, required if all the SAI
66			  registers are big-endian rather than little-endian.
67
68Optional properties (for mx6ul):
69
70  - fsl,sai-mclk-direction-output: This is a boolean property. If present,
71			 indicates that SAI will output the SAI MCLK clock.
72
73Note:
74- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the
75  default synchronous mode (sync Rx with Tx) will be used, which means both
76  transmitter and receiver will send and receive data by following clocks
77  of transmitter.
78- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive.
79
80Example:
81sai2: sai@40031000 {
82	      compatible = "fsl,vf610-sai";
83	      reg = <0x40031000 0x1000>;
84	      pinctrl-names = "default";
85	      pinctrl-0 = <&pinctrl_sai2_1>;
86	      clocks = <&clks VF610_CLK_PLATFORM_BUS>,
87		     <&clks VF610_CLK_SAI2>,
88		     <&clks 0>, <&clks 0>;
89	      clock-names = "bus", "mclk1", "mclk2", "mclk3";
90	      dma-names = "tx", "rx";
91	      dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>,
92		   <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>;
93	      big-endian;
94	      lsb-first;
95};
96